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EMC2300 Fan Control Device with High Frequency PWM and Temperature Monitors
PRODUCT FEATURES
3.3 Volt Operation (5 Volt Tolerant Input Buffers) SMBus 2.0 Compliant Interface (Fixed, not Discoverable) with Three Slave Address Options Fan Control
-- PWM (Pulse width Modulation) Outputs (3) -- Fan Tachometer Inputs (4) -- Programmable automatic fan control based on temperature -- Backwards compatible with fans requiring lower frequency PWM drive -- High frequency fan support for 4 wire fans -- One fan can be controlled from as many as 3 temperature zones -- Fan ramp rate control for acoustic noise reduction
Datasheet Temperature Monitor
-- Monitoring of Two Remote Thermal Diodes (+/- 3 deg C accuracy) -- Internal Ambient Temperature Measurement -- Limit Comparison of all Monitored Values -- Interrupt Pin for out-of-limit Temperature Indication
Voltage Monitor
-- Monitors VCC and VCCP -- Limit Comparison of all Monitored Values -- Interrupt Pin for out-of-limit Voltage Indication
XOR Tree Test Mode 16-Pin SSOP Green, Lead-free Package
Power Savings Modes
-- Two monitoring modes: continuous or cycling (for power savings) -- Two low power modes when monitoring if off: Sleep and Shutdown
ORDER NUMBER(S):
EMC2300-AZC FOR 16 PIN, SSOP PACKAGE (LEAD-FREE) EMC2300-AZC-TR FOR 16 PIN, SSOP PACKAGE (LEAD-FREE, TAPE AND REEL)
2800 UNITS FOR 13 INCH REEL, 97 UNITS PER TUBE
SMSC EMC2300
DATASHEET
Revision 0.2 (06-14-06)
Fan Control Device with High Frequency PWM and Temperature Monitors Datasheet
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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Fan Control Device with High Frequency PWM and Temperature Monitors Datasheet
Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 EMC2300 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 3.3 Pin Functions for EMC2300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Buffer Type Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3V Operation, 5V Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 4 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 4.2 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ratings for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 5 SMBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invalid Protocol Response Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Undefined Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Call Address Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Device Time-Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stretching the SCLK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 16 17 17 17 17 18 18 18 18
Chapter 6 Hardware Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Input Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resetting the EMC2300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Soft Reset (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Continuous Monitoring Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Cycle Monitoring Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Diode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 Shutdown Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 Internal Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.2 External Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 20 20 22 22 23 24 25 26 26 26 26 27 27 27 28 28
6.9
Chapter 7 Fan Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1.1 Limit and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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7.1.2 7.1.3 7.1.4 7.1.5
Device Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Fan Speed Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Speed Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linking Fan Tachometers to PWMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29 30 38 44
Chapter 8 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1 8.2 Undefined Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defined Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 Registers 20-24h: Voltage Reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Registers 25-27h: Temperature Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 Registers 28-2Fh: Fan Tachometer Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4 Registers 30-32h: Current PWM Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.5 Register 3Eh: Company ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.6 Register 3Fh: Version / Stepping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.7 Register 40h: Ready/Lock/Start Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.8 Register 41h: Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.9 Register 42h: Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.10 Registers 44-4Dh: Voltage Limit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.11 Registers 4E-53h: Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.12 Registers 54-5Bh: Fan Tachometer Low Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.13 Registers 5C-5Eh: PWM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.14 Registers 5F-61h: Zone Temperature Range, PWM Frequency . . . . . . . . . . . . . . . . . . . 8.2.15 Register 62h, 63h: PWM Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.16 Registers 64-66h: Minimum PWM Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.17 Registers 67-69h: Zone Low Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.18 Registers 6A-6Ch: Absolute Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.19 Register 6F: XOR Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.20 Register 7Ch: Special Function Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.21 Register 7Eh: Interrupt Enable 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.22 Register 7Fh: Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.23 Register 80h: Interrupt Enable 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.24 Register 81h: TACH_PWM Association Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.25 Register 82h: Interrupt Enable 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.26 Registers 85h-88h: A/D Converter LSbs Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.27 Registers 90h-93h: TachX Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.28 Registers 94h-96h: PWMx Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 49 49 49 50 51 53 53 53 55 56 57 58 59 59 61 63 64 65 65 66 67 68 68 69 70 71 72 72 73
Chapter 9 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.1 9.2 PWM Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SMBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Chapter 10 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Appendix A ADC Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Appendix B Example Fan Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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List of Figures
Figure 2.1 Figure 5.1 Figure 6.3 Figure 7.1 Figure 7.2 Figure 7.4 Figure 7.6 Figure 7.7 Figure 8.11 Figure 9.1 Figure 9.4 Figure 10.1 Figure B.1 Figure B.2 Figure B.3 Figure B.4 Figure B.5 EMC2300 16 Pin SSOP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Address Selection on EMC2300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Automatic Fan Control Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Automatic Fan Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Spin Up Reduction Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Illustration of PWM Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 PWM and Tachometer Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Fan Activity Above Low Temp Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PWMx Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16 Pin SSOP Package Outline and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Fan Drive Circuitry (Apply to PWM Driving Two Fans) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Fan Drive Circuitry (Apply to PWM Driving One Fan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Fan Tachometer Circuitry (Apply to Each Fan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Remote Diode (Apply to Remote2 Lines). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Suggested Minimum Track Width and Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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List of Tables
Table 3.1 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.2 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.1 SMBus Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.2 SMBus Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.3 SMBus Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.4 Modified SMBus Receive Byte Protocol Response to ARA. . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.1 AVG[2:0] Bit Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.2 Conversion Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.3 ADC Conversion Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.4 Low Power Mode Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.5 Min/Max ADC Conversion Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.6 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.1 PWM Ramp Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.2 Minimum RPM Detectable Using 3 Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7.3 Minimum RPM Detectable Using 2 Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.2 Registers 20-24h: Voltage Reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.3 Voltage vs. Register Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.4 Registers 25-27h: Temperature Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.5 Temperature vs. Register Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.6 Registers 28-2Fh: Fan Tachometer Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.7 Registers 30-32h: Current PWM Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.8 PWM Duty vs Register Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.9 Register 3Eh: Company ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.10 Register 3Fh: Version / Stepping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.11 Register 40h: Ready/Lock/Start Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.12 Ready/Lock/Start Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.13 Register 41h: Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.15 Register 42h: Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.17 Registers 44-4Dh: Voltage Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.19 Registers 4E-53h: Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.20 Temperature Limits vs. Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.21 Registers 54-5Bh: Fan Tachometer Low Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.22 Registers 5C-5Eh: PWM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.23 Fan Zone Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.24 Fan Spin-Up Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.25 Registers 5F-61h: Zone Temperature Range, PWM Frequency . . . . . . . . . . . . . . . . . . . . . . . Table 8.26 Register Setting vs. PWM Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.27 Register Setting vs. Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.28 Register 62h, 63h: Min/Off, PWM Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.29 PWM Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.30 Registers 64-66h: Minimum PWM Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.31 PWM Duty vs. Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.32 Registers 67-69h: Zone Low Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.33 Temperature Limit vs. Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.34 Registers 6A-6Ch: Absolute Temperature Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.35 Absolute Limit vs. Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.36 Register 6F: XOR Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.37 Register 7Ch: Special Function Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.39 AVG[2:0] Bit Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.40 Register 7Eh: Interrupt Enable 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.42 Register 7Fh: Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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10 11 15 17 17 18 21 21 22 26 27 28 36 42 43 45 49 49 49 50 50 51 52 53 53 53 54 55 56 57 58 58 59 59 60 61 61 62 62 63 64 64 64 65 65 65 66 66 67 67 68 68
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Table 8.44 Register 80h: Interrupt Enable 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.46 Register 81h: TACH_PWM Association Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.49 Register 82h: Interrupt Enable 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.51 Registers 85h-88h: A/D Converter LSbs Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.53 Registers 94h-96h: PWMx Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 9.1 Timing for PWM[1:3] Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 9.2 SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A.1 Analog-to-Digital Voltage Conversions for Hardware Monitoring Block. . . . . . . . . . . . . . . . . .
69 70 71 72 73 75 76 78
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Chapter 1 General Description
The EMC2300 is an environmental monitoring device with automatic fan control capability. This ACPI compliant device provides hardware monitoring for up to two voltages and three thermal zones, measures the speed of up to four fans, and controls the speed of multiple DC fans using Pulse Width Modulator (PWM) outputs. High frequency and low frequency PWMs are supported. The EMC2300 hardware monitor provides analog inputs for monitoring the processor voltage Vccp. This device has the capability to monitor its own internal VCC power supply, which may be connected to either main power (VCC) or the suspend power well (VTR). The EMC2300 hardware monitor includes support for monitoring three thermal zones: two external and one internal. The external temperatures are measured via thermal diode inputs capable of monitoring remote devices. In addition, the EMC2300 is equipped with an ambient temperature sensor for measuring the internal temperature. Pulse Width Modulators (PWM) control the speed of the fans by varying the output duty cycle of the PWM. Each PWM can be associated with any or all of the thermal zones monitored. As the temperature of the associated zone varies, the PWM duty cycle is adjusted accordingly. The Ramp Rate Control feature controls the rate of change of the PWM output, thereby reducing system noise created by changing the fan speed. The speed of each fan is monitored by a Fan Tachometer input. The measured values are compared to values stored in Limit Registers to detect if a fan has stalled or seized. Fan speed may be under host software control or automatic. In host control mode, the host software continuously monitors temperature and fan speed registers, makes decisions as to desired fan speed and sets the PWM's to drive the required fan speed. This device offers an interrupt output signal (INT#), which may be used to interrupt the host on out-of-limit temperature or voltage condition enabling an ACPI response as opposed to the host software continuously monitoring status. In auto "zone" mode, the logic continuously monitors the temperature and fan speeds and adjusts speeds without intervention from the host CPU. Fan speed is adjusted according to an algorithm using the temperature measured in the selected zone, the high and low limits set by the user, and the current fan speed. The EMC2300 supports two Monitoring modes: Continuous Mode and Cycle Mode. In the continuous monitoring mode, the sampling and conversion process is performed continuously for each voltage and temperature reading after monitoring is enabled. The time for each voltage and temperature reading varies depending on the measurement option. In cycle monitoring mode, the part completes all sampling and conversions, then waits approximately one second to repeat the process. It repeats the sampling and conversion process typically every 1.2 seconds (1.4 sec max - default averaging enabled). The sampling and conversion of each voltage and temperature reading is performed once every monitoring cycle. (This is a power saving mode.) The EMC2300 can be placed in one of two low-power modes: Sleep mode or Shutdown mode. These modes do not reset any of the registers of the device. In Sleep mode bias currents are on and the internal oscillator is on, but the A/D converter and monitoring cycle are turned off. Serial bus communication is still possible with any register in the Hardware Monitor Block while in this low-power mode. In Shutdown mode the bias currents are off, the internal oscillator is off, and the A/D converter and monitoring cycle are turned off. Serial communication is only possible with a select register.
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Chapter 2 Pinout
The EMC2300 is offered in a 16 pin SSOP mechanical package.
2.1
EMC2300 Pinout
SDA SCLK VSS VCC TACH3/INT# PWM2/INT# TACH1 TACH2
1 2 3 4 5 6 7 8 EMC2300
16 15 14 13 12 11 10 9
PWM1/xTestOut Vccp Remote1+ Remote1Remote2+ Remote2TACH4/AddressSelect PWM3/AddressEnable
Figure 2.1 EMC2300 16 Pin SSOP Pinout
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Chapter 3 Pin Description
3.1 Pin Functions for EMC2300
Table 3.1 Pin Description BUFFER REQUIREMENT BUFFER PER FUNCTION POWER TYPE (Note 3.1) WELL
PIN #
NAME
FUNCTION
NOTES
HARDWARE MONITORING BLOCK (16) 1 2 13 SDA SCLK Remote1System Management Bus bi-directional Data. Open Drain output. System Management Bus Clock. This is the negative Analog input (current sink) from the remote thermal diode. This serves as the negative input into the A/D. Digital Input. IMOD3 IM IAN IMOD3 IM IAN VCC VCC VCC
14 11
Remote1+ This is the positive input (current source) from the remote thermal diode. This serves as the positive input into the A/D. Remote2This is the negative Analog input (current sink) from the remote thermal diode. This serves as the negative input into the A/D. Digital Input.
IAN IAN
IAN IAN
VCC VCC
12 15 7 8 5 10
Remote2+ This is the positive input (current source) from the remote thermal diode. This serves as the positive input into the A/D. VCCP TACH1 TACH2 TACH3 /INT# TACH4 /Address Select Analog input for +Vccp (processor voltage: 0 to 3.0V). Input for monitoring a fan tachometer input. Input for monitoring a fan tachometer input. Input for monitoring a fan tachometer input. /Interrupt output to indicate a thermal and/or voltage event. Input for monitoring a fan tachometer input. If in Address Select Mode, determines the SMBus address of the device.
IAN IAN IM IM IMOD3 IM O8 OD8 IOD8
IAN IAN IM IM IM /OD3 IM OD8/O8 OD8/OD8 OD8/I
VCC VCC VCC VCC VCC VCC Note 3.2
16 6 9
PWM1 PWM Output 1 controlling speed of fan. /xTest Out When in XOR tree test mode, functions as XOR Tree output. PWM2 /INT# PWM3 /Address Enable# VCC PWM Output 2 controlling speed of fan. /Interrupt output to indicate a thermal and/or voltage event. PWM Output 3 controlling speed of fan. If pulled to ground at power on, enables Address Select Mode (Address Select pin controls SMBus address of the device). Positive Power Supply. Nominal 3.3V. VCC is monitored by the Hardware Monitoring Block. (Can be powered by +3.3V Standby power if monitoring in low power states is required.)
VCC VCC VCC
4
3
VSS
Analog Ground.
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Note: The "#" as the suffix of a signal name indicates an "Active Low" signal. Note 3.1 Note 3.2 Buffer types per function on multiplexed pins are separated by a slash "/" Buffer types in parenthesis represent multiple buffer types for a single pin function. This analog input is backdrive protected.
3.2
Buffer Type Description
Note: The buffer type values are specified at VCC=3.3V Table 3.2 Buffer Type Descriptions BUFFER TYPE IM IAN IMOD3 O8 OD8 IO8 Digital Input Analog Input, Hardware Monitoring Block Input/Output (Open Drain), 3mA sink. Output, 8mA sink, 4mA source. Output (Open Drain), 8mA sink. Input/Output, 8mA sink, 4mA source. DESCRIPTION
3.3
3.3V Operation, 5V Tolerance
The EMC2300 is intended to operate with a nominal 3.3V power supply. The analog voltage pins are connected to voltage sources at their respective nominal levels. All digital signal pins are 3V switching, but are tolerant to 5V.
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Chapter 4 Operational Description
4.1 Maximum Guaranteed Ratings
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55o to +150oC Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020 Maximum VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V Positive Voltage on any pin (except for analog inputs), with respect to Ground . . . . . . . . . . . . . . 5.5V Negative Voltage on any pin (except for analog inputs), with respect to Ground. . . . . . . . . . . . . . -0.3V Positive Voltage on voltage analog inputs: Vccp_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V Note: Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
4.2
Ratings for Operation
TA = 0oC - 70oC, VCC=+3.3V10%
PARAMETER Temperature-to-Digital Converter Characteristics Internal Temperature Accuracy
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
-3 -2
0.25
+3 +2
oC oC
0oC <= TA <= 70oC 40oC <= TA <= 70oC
External Diode Sensor Accuracy
-5 -3
0.25
+5 +3
oC oC
-40oC <= TS <= 125oC 40oC <= TS <= 100oC
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PARAMETER Analog-to-Digital Converter Characteristics Total Unadjusted Error Differential Non-Linearity Power Supply Sensitivity Total Monitoring Cycle Time (Cycle Mode, Default Averaging) Conversion Time (Continuous Mode, Default Averaging) Input Resistance ADC Resolution Input Buffer (VID0-VID4,TACH1-TACH4) Low Input Level High Input Level IOD Type Buffer (SCL, SDA, PWM1, PWM2, PWM3/ADDRESS ENABLE, INT# Low Input Level High Input Level Hysteresis Low Output Level Leakage Current (ALL - Digital) Input High Current Input Low Current Digital Input Capacitance VCC Supply Current Active Mode Sleep Mode Shutdown Mode Notes:
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
TUE DNL PSS tC(Cycle) 1 1 1.22
2
% LSB %/V
Note 4.1
1.4
sec
Note 4.2
tC(Cts)
203
223
248
msec
Note 4.3
140
200
k 10 bits Note 4.6
VILI VIHI 2.0
0.8 Vcc+0.3
V V
VILI VIHI VHYS VOL 2.0 500
0.8 Vcc+0.3
V V mV
0.4
V
IOL = +4.0 mA (Note 4.5) (Note 4.4)
ILEAKIH ILEAKIL CIN
10 -10 10
A A pF
VIN = VCC VIN = 0V
ICC ICC ICC
3 500 3
mA A A
All outputs open, all inputs transitioning from/to 0V to/from 3.3V.
Voltages are measured from the local ground potential, unless otherwise specified. Typical values are at TA=25C and represent most likely parametric norm.
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Timing specifications are tested at the TTL logic levels, VIL=0.4V for a falling edge and VIH=2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V. Note 4.1 Note 4.2 Note 4.3 Note 4.4 Note 4.5 Note 4.6 TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC. Total Monitoring Cycle Time for cycle mode includes a one second delay plus all temperature conversions and all analog input voltage conversions. See Table 6.2, "Conversion Cycle Timing," on page 21 for conversion cycle timing for all averaging options. Only the nominal default case is shown in this section. All leakage currents are measured with all pins in high impedance. The low output level for PWM pins is actually +8.0mA. The h/w monitor analog block implements a 10-bit ADC. The output of this ADC goes to an averager block, which can be configured to accumulate the averaged value of the analog inputs. The amount of averaging is programmable. The output of the averaging block produces a 12-bit temperature or voltage reading value. The 8 MSbits go to the reading register and the 4 LSbits to the A/D LSb register.
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Chapter 5 SMBus Interface
The host processor communicates with the Fan Monitoring device through a series of read/write registers via the SMBus interface. SMBus is a serial communication protocol between a computer host and its peripheral devices.
5.1
Slave Address
The default Slave Address is 0101110b. If this address is desired, the designer should not ground the Address Enable# pin and should not apply a strapping resistor to the Address Select pin. If multiple devices are implemented in a system or another SMBus device requires address 0101110b, TACH4 and PWM3 must be disabled. In this case, addressing is implemented as follows: The board designer will apply a 10K pull-down resistor to ground on the Address Enable# pin. Upon power up, the EMC2300 device will be placed into Address Enable mode and assign itself an SMBus address according to the Address Select input. The device will latch the address during the first valid SMBus transaction in which the first five bits of the targeted address match those of the EMC2300 address. This feature eliminates the possibility of a glitch on the SMBus interfering with address selection. Table 5.1 SMBus Slave Address Options
ADDRESS ENABLE# 1
ADDRESS SELECT X
BOARD IMPLEMENTATION Address Enable# pulled to VCC through resistor Note: Resistor value will be dependent on PWM circuit implemented.
SMBUS ADDRESS [7:1] 0101 110b (default)
0
0
Address Enable# pulled to ground through 10k resistor Address Select Pulled to ground through a 10k resistor Address Enable# pulled to ground through 10k resistor Address Select pulled to VCC through a 10k resistor
0101 100b
0
1
0101 101b
In this way, there can be up to three EMC2300 devices on the SMBus at any time. Multiple EMC2300 devices can be used to monitor additional processors and temperature zones.
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Address Decided Start 0 1 0 1 1
SDA SCL First five address bits
Figure 5.1 Address Selection on EMC2300
5.2
Slave Bus Interface
The EMC2300 device SMBus implementation is a subset of the SMBus interface to the host. The device is a slave-only SMBus device. The implementation in the device is a subset of SMBus since it only supports Write Byte and Read Byte protocols. The Write Byte and Read Byte protocols are valid SMBus protocols for the device. This part responds to other protocols as described in the Invalid Protocol Section. Reference the System Management Bus Specification, Rev 2.0. The SMBus interface is used to read and write the registers in the device. The register set is shown in Chapter 8, "Register Set," on page 45.
5.3
Bus Protocols
Typical Write Byte and Read Byte protocols are shown below. Register accesses are performed using 7-bit slave addressing, an 8-bit register address field, and an 8-bit data field. The shading indicates the Hardware Monitor Block driving data on the SDA line; otherwise, host data is on the SDA line. The slave address is the unique SMBus Interface Address for the Hardware Monitor Block that identifies it on SMBus. The register address field is the internal address of the register to be accessed. The register data field is the data that the host is attempting to write to the register or the contents of the register that the host is attempting to read. Note: Data bytes are transferred MSB first. Byte Protocols A write byte transfer will always consist of the SMBus Interface Address byte, followed by the Internal Address Register byte, then the data byte. The normal read protocol consists of a write to the Hardware Monitor Block with the SMBus Interface Address byte, followed by the Internal Address Register byte. Then restart the Serial Communication with a Read consisting of the SMBus Interface Address byte, followed by the data byte read from the Hardware Monitor Block. This can be accomplished by using the Read Byte protocol. Write Byte The Write Byte protocol is used to write data to the registers. The data will only be written if the protocol shown in Table 5.2 is performed correctly. Only one byte is transferred at time for a Write Byte protocol.
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Table 5.2 SMBus Write Byte Protocol FIELD Bits START 1 Read Byte The Read Byte protocol is used to read data from the registers. The data will only be read if the protocol shown in Table 5.3 is performed correctly. Only one byte is transferred at time for a Read Byte protocol. Table 5.3 SMBus Read Byte Protocol
FIELD: START 1 SLAVE ADDR 7 WR 1 ACK 1 REG. ADDR 8 ACK 1 START 1 SLAVE ADDR 7 RD 1 ACK 1 REG. DATA 8 NACK 1 STOP 1
SLAVE ADDR 7
WR 1
ACK 1
REG. ADDR 8
ACK 1
REG. DATA 8
ACK 1
STOP 1
Bits:
5.4
Invalid Protocol Response Behavior
Registers that are accessed with an invalid protocol will not be updated. A register will only be updated following a valid protocol. The only valid protocols are the Write Byte and Read Byte protocols, which are described above. The EMC2300 device responds to three SMBus slave addresses: 1. The SMBus slave address that supports the valid protocols defined in the previous sections is determined by the level on the Address Select and Address Enable pins as shown in Section 5.1, "Slave Address," on page 15. 2. SMBus Alert Response (0001 100). The SMBus will only respond to the SMBus Alert Response Address if the SMBus Alert Response interrupt was generated to request a response from the Host. The SMBus Alert Response is defined in Section 5.10, "SMBus Alert Response Address," on page 18. Attempting to communicate with the Hardware Monitor Block over SMBus with an invalid slave address, or invalid protocol will result in no response, and the SMBus Slave Interface will return to the idle state. The only valid registers that are accessible by the SMBus slave address are the registers defined in the Registers Section. See Section 5.4.1, "Undefined Registers" for response to undefined registers.
5.4.1
Undefined Registers
Reads to undefined registers return 00h. Writes to undefined registers have no effect and return no error.
5.5
General Call Address Response
The EMC2300 will not respond to a general call address of 0000_000.
5.6
Slave Device Time-Out
The EMC2300 supports the slave device timeout as per the SMBus Specification, v2.0.
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According to SMBus specification, v2.0 devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds 25ms (TTIMEOUT, MIN). Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than 35ms (TTIMEOUT, MAX). Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port after a start or stop condition
5.7
Stretching the SCLK Signal
The EMC2300 supports stretching of the SCLK by other devices on the SMBus but will not stretch the SCLK itself.
5.8
SMBus Timing
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing diagram shown in the section titled Section 9.2, "SMBus Interface," on page 76.
5.9
Bus Reset Sequence
The SMBus Slave Interface will reset and return to the idle state upon a START field followed immediately by a STOP field.
5.10
SMBus Alert Response Address
The EMC2300 device responds to the SMBus Alert Response Address, 0001 100, if the INTEN bit (register 7Ch bit 2) is set and one or more status events bits are high. The interrupt signal (INT#), which can be enabled on either the PWM2 or TACH3 pins, can be used as the SMBALERT#. See the section describing the Interrupt Status Registers on page 23 and the section describing the Interrupt Pin on page 25 for more details on interrupts. The device can signal the host that it wants to talk by pulling the SMBALERT# low, if a status bit is set in one of the interrupt status registers and properly enabled onto the INT# pin. The host processes the interrupt and simultaneously accesses all SMBALERT# devices through a modified Receive Byte operation with the Alert Response Address (ARA). The EMC2300 device, which pulled SMBALERT# low, will acknowledge the Alert Response Address and respond with its device address. The 7-bit device address provided by the EMC2300 device is placed in the 7 most significant bits of the byte. The eighth bit can be a zero or one. Table 5.4 Modified SMBus Receive Byte Protocol Response to ARA ALERT RESPONSE ADDRESS 7
FIELD: Bits:
START 1
RD 1
ACK 1
EMC2300 SLAVE
ADDRESS 8
NACK 1
STOP 1
After acknowledging the slave address, the EMC2300 device will disengage the SMBALERT# pull-down by clearing the INT enable bit. If the condition that caused the interrupt remains, the Fan Control device will reassert the SMBALERT# on the next monitoring cycle, provided the INT enable bit has been set back to `1' by software. Note: The INT# signal is an alternate function on the PWM2 and TACH3 pins. The EMC2300 device will respond to the SMBus Alert Response address even if the INT# signal is not selected as the alternate function on one of these pins as long as the following conditions exist: the INTEN
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bit (register 7Ch bit 2) is set, an individual status bit is set in one of the interrupt status registers, and the corresponding group enable bit is set. Each interrupt event must be enabled into the interrupt status registers, and the status bits must be enabled onto the INT# signal via the group enable bits for each type of event (i.e., temperature, voltage and fan). See the section titled Interrupt Status Registers on page 23.
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Chapter 6 Hardware Monitoring
The following sub-sections describe the EMC2300 Hardware Monitoring features.
6.1
Input Monitoring
The EMC2300 device's monitoring function is started by writing a `1' to the START bit in the Ready/Lock/Start Register (0x40). Measured values from the analog inputs and temperature sensors are stored in Reading Registers. The values in the reading registers can be accessed via the SMBus interface. These values are compared to the programmed limits in the Limit Register. The out-of-limit and diode fault conditions are stored in the Interrupt Status Registers.
6.2
6.2.1
Resetting the EMC2300
Power-On Reset
All the registers in the Hardware Monitor Block, except the reading registers, reset to a default value when power is applied to the block. The default state of the register is shown in the table in the Register Summary subsection. The default state of Reading Registers are not shown because these registers have indeterminate power on values. Note: Usually the first action after power up is to write limits into the Limit Registers.
6.2.2
Soft Reset (Initialization)
Setting bit 7 of the CONF register performs a soft reset. This bit is self-clearing. Soft Reset performs reset on all the registers except the Reading Registers.
6.3
Monitoring Modes
The Hardware Monitor Block supports two Monitoring modes: Continuous Mode and Cycle Mode. These modes are selected using bit 1 of the Special Function Register (7Ch). The following subsections contain a description of these monitoring modes. The hardware monitor conversion clock is 45KHz 10%. Temperature conversions take 96 clocks, each (2.133ms nom.); voltage conversions take 68 clocks, each (1.511ms nom). The time to complete a conversion cycle depends upon the number of inputs in the conversion sequence to be measured (see Table 6.3, "ADC Conversion Sequence," on page 22) and the amount of averaging per input, which is selected using the AVG[2:0] bits in the Special Function register (see Register 7Ch: Special Function Register on page 67). For each mode, there are four options for the number of measurements that are averaged for each temperature and voltage reading. These options are selected using bits[7:5] of the Special Function register (7Ch). These bits are defined as follows:
Bits [7:5] AVG[2:0]
The AVG[2:0] bits determine the amount of averaging for each of the measurements that are performed by the hardware monitor before the reading registers are updated (Table 6.1). The AVG[2:0] bits are priority encoded where the most significant bit has highest priority. For example, when the AVG2 bit is asserted, 32 averages will be performed for each measurement before the reading registers are updated regardless of the state of the AVG[1:0] bits.
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Table 6.1 AVG[2:0] Bit Decoder SFTR[7:5] REMOTE DIODE 1 128 16 16 32 MEASUREMENTS PER READING REMOTE DIODE 2 128 16 16 32 INTERNAL DIODE 8 1 16 32 ALL VOLTAGE READINGS (VCCP, AND VCC) 8 1 16 32
AVG2 0 0 0 1
AVG1 0 0 1 X
AVG0 0 1 X X
Note: The default for the AVG[2:0] bits is `010'b. To calculate conversion cycle timing for a given averaging mode: Compute total number of temperature conversions (TEMP_CONV) Compute total number of voltage conversions (VOLT_CONV) Calculate Time to complete all conversions is: Total Conversion Time = (TEMP_CONV)*96/(45kHz +/-10%)+ (VOLT_CONV)*68/(45kHz +/-10%) Example: To calculate the nominal conversion time FOR AVG[2:0] = 001b. Total Conversion Time = (TEMP_CONV)*96/(45kHz)+ (VOLT_CONV)*68/(45kHz) Total Conversion Time = (16+16+1)*96/(45kHz)+ (2*1)*68/(45kHz) Total Conversion Time = (33)*2.133ms+ (2)*1.511ms = ~73ms Table 6.2 illustrates the min., nom., and max. conversion cycle timing for each of the four averaging modes. Table 6.2 Conversion Cycle Timing TOTAL TEMPERATURE CONVERSIONS (2x128)+(1x8)=264 (2x16)+(1x1)=33 3x16=48 3x32=96 Note 6.1 Note 6.2 TOTAL VOLTAGE CONVERSIONS 2x8=16 2x1=2 2x16=32 2x32=64 CONVERSION CYCLE TIME (MSEC) MIN. 536 67 191 382 NOM. 587 73 210 420 MAX. 652 82 233 466
AVG[2:0] 000 001 01X (default) 1XX
The hardware monitor conversion clock is 45KHz 10%. Temperature conversions take 96 clocks, each (2.133ms nom.); Voltage conversions take 68 clocks, each (1.511ms nom).
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6.3.1
Continuous Monitoring Mode
In the continuous monitoring mode, the sampling and conversion process is performed continuously for each voltage and temperature reading after the Start bit is set high. The time for each voltage and temperature reading is shown above for each measurement option. The continuous monitoring function is started by doing a write to the Ready/Lock/Start Register, setting the Start bit (Bit 0) high. The part then performs a "round robin" sampling of the inputs, in the order shown below (see Table 6.3). Sampling of all values occurs in a nominal 210ms (default - see Table 6.2, "Conversion Cycle Timing," on page 21). Table 6.3 ADC Conversion Sequence SAMPLING ORDER 1 2 3 4 5 REGISTER Remote Diode Temp Reading 1 Ambient Temperature reading VCC reading Vccp (processor) reading Remote Diode Temp Reading 2
When the continuous monitoring function is started, it cycles through each measurement in sequence, and it continuously loops through the sequence approximately once every 210ms (default - see Table 6.2, "Conversion Cycle Timing," on page 21). Each measured value is compared to values stored in the Limit registers. When the measured value violates the programmed limit the Hardware Monitor Block will set a corresponding status bit in the Interrupt Status Registers. If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See Auto Fan Control Operating Mode on page 31. The results of the sampling and conversions can be found in the Reading Registers and are available at any time.
6.3.2
Cycle Monitoring Mode
In cycle monitoring mode, the part completes all sampling and conversions, then waits approximately one second to repeat the process. It repeats the sampling and conversion process typically every 1.2 seconds (1.4 sec max - default averaging enabled). The sampling and conversion of each voltage and temperature reading is performed once every monitoring cycle. This is a power saving mode. The cycle monitoring function is started by doing a write to the Ready/Lock/Start Register, setting the Start bit (Bit 0) high. The part then performs a "round robin" sampling of the inputs, in the order shown above. When the cycle monitoring function is started, it cycles through each measurement in sequence, and it produces a converted voltage and temperature reading for each input. The state machine waits approximately one second before repeating this process. Each measured value is compared to values stored in the Limit registers. When the measured value violates (or is equal to) the programmed limit the Hardware Monitor Block will set a corresponding status bit in the Interrupt Status Registers. If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See the section titled Auto Fan Control Operating Mode on page 31. The results of each sampling and conversion can be found in the Reading Registers and are available at any time, however, they are only updated once per conversion cycle.
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6.4
Interrupt Status Registers
The Hardware Monitor Block contains two interrupt status registers: Register 41h: Interrupt Status Register 1 on page 55 and Register 42h: Interrupt Status Register 2 on page 56. These registers are used to reflect the state of all temperature, voltage and fan violation of limit error conditions and diode fault conditions that the Hardware Monitor Block monitors. When an error occurs during the conversion cycle, its corresponding bit is set in its respective interrupt status register. The bit remains set until the register is read by software, at which time the bit will be cleared to `0' if the associated error event no longer violates the limit conditions or if the diode fault condition no longer exists. Reading the register will not cause a bit to be cleared if the source of the status bit remains active. These registers are read only - a write to these registers have no effect. These registers default to 0x00 on VCC POR and Initialization. See the description of the Interrupt Status registers in Chapter 8, "Register Set," on page 45. Each interrupt status bit has a corresponding bit located in an interrupt enable register, which may be used to enable/disable the individual event from setting the status bit. See the following figure for the status and enable bits used to control the interrupt bits and INT# pin.
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INT_STS1 Reg
Vccp_Error Vccp_Error_En (IER1[3]) VCC_Error VCC_Error_En (IER1[7])
Vccp_Error (INT1[1]) + VOLTAGE_EN (IER1[0]) + TEMP_EN (IER3[0]) VCC_Error (INT1[2])
Diode 1 Limit Diode 1_En (IER3[2]) Ambient Limit Ambient_En (IER3[1]) Diode 2 Limit Diode 2_En (IER3[3])
Diode 1 Limit (INT1[4]) Ambient Limit (INT1[5]) Diode 2 Limit (INT1[6]) INT2 (INT1[7])
+ INT_EN (SFTR[2])
INT#
INT_STS2 Reg
TACH1 Out-of-Limit TACH1_En (IER2[1]) TACH2 Out-of-Limit TACH2 _En (IER2[2]) TACH3 Out-of-Limit TACH3 _En (IER2[3]) TACH4 Out-of-Limit TACH4 _En (IER2[4]) Diode 1 Fault Diode 1_En (IER3[2]) Diode 2 Fault Diode 2_En (IER3[3])
TACH1 (INT2[2]) TACH2 (INT2[3]) + TACH_EN (IER2[0])
TACH3 (INT2[4]) TACH4 (INT2[5]) Diode 1 Fault (INT2[6]) Diode 2 Fault (INT2[7])
Figure 6.3 Interrupt Control Note: The diode fault bits are not mapped directly to the INT# pin. A diode fault condition forces the diode reading register to a value of 80h, which will generate a Diode Error condition. See section Diode Fault on page 24.
6.4.1
Diode Fault
The EMC2300 Chip automatically sets the associated diode fault bit to 1 when any of the following conditions occur on the Remote Diode pins: The positive and negative terminal are an open circuit. Positive terminal is connected to VCC Positive terminal is connected to ground Negative terminal is connected to VCC Negative terminal is connected to ground
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The occurrence of a fault will cause 80h to be loaded into the associated reading register, except for the case when the negative terminal is connected to ground. A temperature reading of 80h will cause the corresponding diode error bit to be set. This will cause the INT# pin to become active if the individual, group (TEMP), and global enable (INTEN) bits are set. Notes: The individual remote diode enable bits and the TEMP bit are located inTable 8.50 on page 71. The INTEN bit is located in bit[2] of Register 7Ch: Special Function Register on page 67. When 80h is loaded into the Remote Diode Reading Register the PWM output(s) controlled by the zone associated with that diode input will be forced to full on. See Thermal Zones on page 28. If the diode is disabled, the fault bit in the interrupt status register will not be set. In this case, the occurrence of a fault will cause 00h to be loaded into the associated reading register. The limits must be programmed accordingly to prevent unwanted fan speed changes based on this temperature reading. If the diode is disabled and a fault condition does not exist on the diode pins, then the associated reading register will contain a "valid" reading.
6.5
Interrupt Pin
The INT# function is used as an interrupt output for out-of-limit temperature, voltage events, and/or fan errors. The INT# signal can be enabled onto the PWM2 or the TACH3 pins. To configure the PWM2/INT# pin for the interrupt function, set bit[1] P2INT of the CONF register (7Fh) to `1' To configure the TACH3/INT# pin for the interrupt function, set bit[0] T3INT of the CONF register (7Fh) to `1' To enable the interrupt pin to go active, set bit 2 of the Special Function Register (7Ch) to `1'. To enable temperature event, voltage events and/or fan events onto the INT# pin: To enable out-of-limit temperature events set bit[0] of the Interrupt Enable 3 (TEMP) register (82h) to `1'. To enable out-of-limit voltage events set bit[0] of the Interrupt Enable 1(VOLT) register (7Eh) to `1' To enable Fan tachometer error events set bit[0] of the Interrupt Enable 2(Fan Tachs) register (80h) to `1'. See Figure 6.3 on page 24. The following description assumes that the interrupt enable bits for all events are set to enable the interrupt status bits to be set. If the internal or remote temperature reading violates the low or high temperature limits, INT# will be forced active low (if all the corresponding enable bits are set: individual enable bits (D1_EN, D2_EN, and/or AMB_EN), group enable bit (TEMP_EN) and the global enable bit (INTEN)). This pin will remain low while the Internal Temp Error bit or one or both of the Remote Temp Error bits in Interrupt Status 1 Register is set and the enable bit is set. The INT# pin will not become active low as a result of the remote diode fault bits becoming set. However, the occurrence of a fault will cause 80h to be loaded into the associated reading register, which will cause the corresponding diode error bit to be set. This will cause the INT# pin to become active if enabled. The INT# pin can be enabled to indicate out-of-limit voltages. Bit[0] of the Interrupt Enable 1(VOLT) register (7Eh) is used to enable this option. When this bit is set, if one or more of the voltage readings violates the low or high limits, INT# will be forced active low (if all the corresponding enable bits are set: individual enable bits (VCC_Error_En, VCCP_Error_En), group enable (VOLT_EN), and global enable (INT_EN)). This pin will remain low while the associated voltage error bit in the Interrupt Status Register 1 or Interrupt Status Register 2 is set.
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The INT# pin can be enabled to indicate fan errors. Bit[0] of the Interrupt Enable 2(Fan Tachs) register (80h) is used to enable this option. This pin will remain low while the associated fan error bit in the Interrupt Status Register 2 is set. The INT# pin will remain low while any bit is set in any of the Interrupt Status Registers. Reading the interrupt status registers will cause the logic to attempt to clear the status bits; however, the status bits will not clear if the interrupt stimulus is still active. The interrupt enable bit (Special Function Register bit[2]) should be cleared by software before reading the interrupt status registers to insure that the INT# pin will be re-asserted while an interrupt event is active, when the INT_EN bit is written to `1' again. The INT# pin can also be deasserted by issuing an Alert Response Address Call. See the description in the section titled SMBus Alert Response Address on page 18. The INT# pin may only become active while the monitor block is operational.
6.6
Low Power Modes
The Hardware Monitor Block can be placed in a low-power mode by writing a `0' to Bit[0] of the Ready/Lock/Start Register (0x40). The low power mode that is entered is either sleep mode or shutdown mode as selected using Bit[0] of the Special Function Register (7Ch). These modes do not reset any of the registers of the Hardware Monitor Block. In both of these modes, the PWM pins are at 100% duty cycle. Table 6.4 Low Power Mode Control Bits START 0 0 1 Notes: START and LPMD bits cannot be modified when the LOCK bit is set. START bit is located in the Ready/Lock/Start register (40h). LPMD bit is located in the Special Function Register (7Ch) LPMD 0 1 x Sleep Mode Shutdown Mode Monitoring DESCRIPTION
6.6.1
Sleep Mode
This is a low power mode in which bias currents are on and the internal oscillator is on, but the A/D converter and monitoring cycle are turned off. Serial bus communication is still possible with any register in the Hardware Monitor Block while in this low-power mode.
6.6.2
Shutdown Mode
This is a low power mode in which bias currents are off, the internal oscillator is off, and the the A/D converter and monitoring cycle are turned off. Serial communication is only possible with Bits[2:0] of the Special Function Register at 7Ch and Bits [7:0] of the Configuration Register at 7Fh, which become write-only registers in this mode.
6.7
Analog Voltage Measurement
The Hardware Monitor Block contains inputs for directly monitoring the power supplies (Vccp, and VCC). These inputs are scaled internally to an internal reference source, converted via an 8 bit successive approximation register ADC , and scaled such that the correct value refers to 3/4 scale or 192 decimal. The VCCP input is scaled for a full range of 0V to 3V.
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The measured values are stored in the Reading registers and compared with the Limit registers. The status bits in the Interrupt Status Register 1 and 2 are set if the measured values violate the programmed limits. The Vccp voltage input measures the processor voltage, which will lie in the range of 0V to 3.0V. Table 6.5, "Min/Max ADC Conversion Table" shows the values of the analog inputs that correspond to the min and max output codes of the A/D converter. For a complete list of the ADC conversions see Appendix A, "ADC Voltage Conversion," on page 78. Table 6.5 Min/Max ADC Conversion Table INPUT VOLTAGE Min Value (Corresponds to A/D output 00000000) Max Value (Corresponds to A/D output 11111111) VCC <0.017 >4.383 +VCCP <0.012 >2.988
6.8
Temperature Measurement
Temperatures are measured internally by bandgap temperature sensor and externally using two sets of diode sensor pins (for measuring two external temperatures). See subsections below. Note: The temperature sensing circuitry for the two remote diode sensors is calibrated for a 3904 type diode.
6.8.1
Internal Temperature Measurement
Internal temperature can be measured by bandgap temperature sensor. The measurement is converted into digital format by internal ADC. This data is converted in two's complement format since both negative and positive temperature can be measured. This value is stored in Internal Temperature Reading register (26h) and compared to the Temperature Limit registers (50h - 51h). If this value violates the programmed limits in the Internal High Temperature Limit register (51h) or the Internal Low Temperature Limit register (50h) the corresponding status bit in Interrupt Status Register 1 is set. If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See the section titled Auto Fan Control Operating Mode on page 31.
6.8.2
External Temperature Measurement
The Hardware Monitor Block also provides a way to measure two external temperatures using diode sensor pins (Remote x+ and Remote x-). The value is stored in the register (25h) for Remote1+ and Remote1- pins. The value is stored in the Remote Temperature Reading register (27h) for Remote2+ and Remote2- pins. If these values violate the programmed limits in the associated limit registers, then the corresponding Remote Diode 1 (D1) or Remote Diode 2 (D2) status bits will be set in the Interrupt Status Register 1. If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See Auto Fan Control Operating Mode on page 31. There are Remote Diode (1 or 2) Fault status bits in Interrupt Status Register 2 (42h), which, when set to a logical `1', indicate a short or open-circuit on remote thermal diode inputs (Remote x+ and Remote x-). Before a remote diode conversion is updated, the status of the remote diode is checked. In the case of a short or open-circuit on the remote thermal diode inputs, the value in the corresponding reading register will be forced to 80h. Note that this will cause the associated remote diode limit exceeded status bit to be set (i.e. Remote Diode x Limit Error bits (D1 and D2) are located in the Interrupt Status 1 Register at register address 41h).
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The temperature change is computed by measuring the change in Vbe at two different operating points of the diode to which the Remote x+ and Remote x- pins are connected. But accuracy of the measurement also depends on non-ideality factor of the process the diode is manufactured on.
6.8.3
Temperature Data Format
Temperature data can be read from the three temperature registers: Internal Temp Reading register (26h) Remote Diode 1 Temp Reading register (25h) Remote Diode 2 Temp Reading register (27h) Table 6.6, "Temperature Data Format" shows several examples of the format of the temperature digital data, represented by an 8-bit, two's complement word with an LSB equal to 1.0 0C. Table 6.6 Temperature Data Format
TEMPERATURE -1270C ...
READING (DEC) -127 ...
READING (HEX) 81h ...
DIGITAL OUTPUT 1000 0001 ... 1100 1110 ... 1110 0111 ... 1111 1111 0000 0000 0000 0001 ... 0001 1001 ... 0011 0010 ... 0111 1111 1000 0000
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-50 0C ...
-50 ...
CEh ... E7h ...
-25 0C ...
-25 ... -1 0 1 ...
-1 0C 0 0C +1 0C ...
FFh 00h 01h ... 19h ... 32h ... 7Fh 80h
+25 0C ...
25 ... 50 ... 127 128
+500C ... +1270C SENSOR ERROR
6.9
Thermal Zones
Each temperature measurement input is assigned to a Thermal Zone to control the PWM outputs in Auto Fan Control mode. These zone assignments are as follows: Zone 1 = Remote Diode 1 (Processor) Zone 2 = Ambient (Internal) Temperature Sensor Zone 3 = Remote Diode 2
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Chapter 7 Fan Control
The following sections describe the various fan control and monitoring modes in the part.
7.1
General Description
This Fan Control device is capable of driving multiple DC fans via three PWM outputs and monitoring up to four fans equipped with tachometer outputs in either Manual Fan Control mode or in Auto Fan Control mode. The three fan control outputs (PWMx pins) are controlled by a Pulse Width Modulation (PWM) scheme. The four pins dedicated to monitoring the operation of each fan are the TACH[1:4] pins. Fans equipped with Fan Tachometer outputs may be connected to these pins to monitor the speed of the fan.
7.1.1
Limit and Configuration Registers
At power up, all the registers are reset to their default values and PWM[1:3] are set to "Fan always on Full" mode. Before initiating the monitoring cycle for either manual or auto mode, the values in the limit and configuration registers should be set. The limit and configuration registers are: Registers 54h - 5Bh: TACHx Minimum Registers 5Fh - 61h: Zone x Range/FANx Frequency Registers 5Ch - 5Eh: PWMx Configuration Registers 62h - 63h: PWM x Ramp Rate Control Registers 64h - 66h: PWMx Minimum Duty Cycle Registers 67h - 69h: Zone x Low Temp LIMIT Registers 6Ah - 6Ch: Zone x Temp Absolute Limit - all fans in Auto Mode are set to full Register 81h: TACH_PWM Association Registers 90h - 93h: Tachx Option Registers Registers 94h - 96h: PWMx Option Registers The limit and configuration registers are defined in Chapter 8, Register Set. Notes: The START bit in Register 40h Ready/Lock/Start Register must be set to `1' to start temperature monitoring functions. Setting the PWM Configuration register to Auto Mode will not take effect until after the START bit is set
7.1.2
Device Set-Up
BIOS will follow the steps listed below to configure the fan registers on this device. The registers corresponding to each function are listed. All steps may not be necessary if default values are acceptable. Regardless of all changes made by the BIOS to the limit and parameter registers during configuration, the EMC2300 will continue to operate based on default values until the Start bit, in the Ready/Lock/Start register, is set. Once the Start bit is set, the EMC2300 will operate according to the values that were set by BIOS in the limit and parameter registers. 1. Set limits and parameters (not necessarily in this order) 2. [5F-61h] Set PWM frequencies and Auto Fan Control Range. 3. [62-63h] Set Ramp Rate Control
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4. [5C-5Eh] Set the fan spin-up delays. 5. [5C-5Eh] Match each PWM output with a corresponding thermal zone. 6. [67-69h] Set the zone temperature low limits. 7. [6A-6Ch] Set the zone temperature absolute limits. 8. [64-66h] Set the PWM minimum duty cycle. 9. [81h] Associate a Tachometer input to a PWM output Register 10. [90-93h] Select the TACH Mode of operation (Mode 1 or Mode 2) 11. [90-93h] Set the number of edges per tach reading 12. [90-93h] Set the ignore first 3 edges of tach input bit 13. [90-93h] Set the SLOW bit to 0b if tach reading should indicated slow fan event as FFFEh and 1b if stalled fan event as FFFFh. 14. [94-96h] Set the TACH Reading Update rate 15. [94-96h] Set the tach reading guard time (Mode 2 Only) 16. [94-96h] Set the TACH reading logic for Opportunistic Mode (Mode 2 Only) 17. [94-96h] Set the SZEN bit, which determines if the PWM output will ramp to Off or jump to Off. 18. [40h] Set bit 0 (Start) to start monitoring. 19. [40h] Set bit 1 (Lock) to lock the limit and parameter registers (optional)
7.1.3
PWM Fan Speed Control
Note: The following description applies to PWM1, PWM2, and PWM3. When describing the operation of the PWMs, the terms "Full on" and "100% duty cycle" means that the PWM output will be high for 255 clocks and low for 1 clock (INVERT bit = 0). The exception to this is during fan spin-up when the PWM pin will be forced high for the duration of the spin-up time.
7.1.3.1
Manual Fan Control Operating Mode (Test Mode)
When operating in Manual Fan Control Operating Mode, software controls the speed of the fans by directly programming the PWM duty cycle. The operation of the fans can be monitored based on reading the temperature and tachometer reading registers and/or by polling the interrupt status registers. The EMC2300 offers the option of generating an interrupt indicated by the INT# signal located on the PWM2 and TACH3 pins. To control the PWM outputs in manual mode: Write `111' to bits[7:5] Zone/Mode, located in Registers 5Ch-5Eh: PWMx Configuration. The speed of the fan is controlled by the duty cycle set for that PWM output. The duty cycle must be programmed in Registers 30h-32h: Current PWM Duty To monitor the fans: Fans equipped with Tachometer outputs can be monitored via the TACHx input pins. See Section 7.1.4, "Fan Speed Monitoring," on page 38. If an out-of-limit condition occurs, the corresponding status bit will be set in the Interrupt Status registers. Setting this status bit will generate an interrupt signal on the INT# pin (if enabled). Software must handle the interrupt condition and modify the operation of the device accordingly. Software can evaluate the operation of the Fan Control device through the Temperature and Fan Tachometer Reading registers. When in manual mode, the current PWM duty cycle registers can be written to adjust the speed of the fans, when the start bit is set. These registers are not writable when the lock bit is set.
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Note: The PWMx Current Duty Cycle register is implemented as two separate registers: a read-only and a write-only. When a value is written to this register in manual mode there will be a delay before the programmed value can be read back by software. The hardware updates the readonly PWMx Current Duty Cycle register on the beginning of a PWM cycle. If Ramp Rate Control is disabled, the delay to read back the programmed value will be from 0 seconds to 1/(PWM frequency) seconds. Typically, the delay will be 1/(2*PWM frequency) seconds.
7.1.3.2
Auto Fan Control Operating Mode
The EMC2300 implements automatic fan control. In Auto Fan Mode, this device automatically adjusts the PWM duty cycle of the PWM outputs, according to the flow chart on the following page (see Figure 7.1 Automatic Fan Control Flow Diagram on page 32). PWM outputs are assigned to a thermal zone based on the PWMx Configuration registers (see Section 6.9, "Thermal Zones," on page 28). It is possible to have more than one PWM output assigned to a thermal zone. For example, PWM outputs 2 and 3, connected to two chassis fans, may both be controlled by thermal zone 2. At any time, if the temperature of a zone exceeds its absolute limit, all PWM outputs go to 100% duty cycle to provide maximum cooling to the system (except those fans that are disabled or in manual mode). It is possible to have a single fan controlled by multiple zones, turning on when either zone requires cooling based on its individual settings. A VCC POR resets all values to their initial or default states. If the start bit is one, the Auto Fan Control block will evaluate the temperature in the zones configured for each Fan in a round robin method. The Auto Fan Control block completely evaluates the zones for all three fans in a maximum of 0.25sec.
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AutoFanMode Initiated
EndPollingCycle
No EndFanSpinUp BeginPolling Cycle
SpinUp TimeElapsed? (5C-5E)
Yes
FanSpinningUp? Yes No Overrideall PWM outputs to100% dutycycleexceptif disabledorin manual mode
Yes
Temp>= AbsLimit (6A~6C)
No
SetFanOutputto 100%
T emp>=Low Limit (67~69)
No
Yes
BeginFanSpin-Up
Yes
MinPWM at0%?
Setfantomin PWM (64~66)
No
Setfanspeedbasedon AutoFanRange Algorithm*
Figure 7.1 Automatic Fan Control Flow Diagram *See Registers 5C-5Eh: PWM Configuration on page 59 for details. When in Auto Fan Control Operating Mode the hardware controls the fans directly based on monitoring of temperature and speed. To control the fans: Set the minimum temperature that will activate the Automatic Fan control algorithm. This value is programmed in Registers 67h-69h: Zone x Low Temp Limit (Auto Fan Mode Only). The speed of the fan is controlled by the duty cycle set for that device. The duty cycle for the minimum fan speed must be programmed in Registers 64h-66h: PWMx Minimum Duty Cycle. This value corresponds to the speed of the fan when the temperature reading is equal to the minimum temperature LIMIT setting. As the actual temperature increases and is above the Zone LIMIT temperature and below the Absolute Temperature Limit, the PWM will be determined by a linear function based on the Auto Fan Speed Range bits in Registers 5Fh-61h.
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Set the absolute temperature for each zone in Registers 6Ah-6Ch: Zone x Temp Absolute Limit (Auto Fan Mode only). If the actual temperature is equal to or exceeds the absolute temperature in one or more of the associated zones, all Fans operating in auto mode will be set to Full on, regardless of which zone they are operating in (except those that are disabled or configured for Manual Mode). Note: Fans can be disabled via the PWMx Configuration registers and the absolute temperature safety feature can be disabled by writing 80h into the Zone x Temp Absolute Limit registers. To set the mode to operate in auto mode, set Bits[7:5] Zone/Mode, located in Registers 5Ch-5Eh: PWM Configuration Bits[7:5]='000' for PWM on Zone 1; Bits[7:5]='001' for PWM on Zone 2; Bits[7:5]='010' for PWM on Zone 3. If the "Hottest" option is chosen (101 or 110), then the PWM output is controlled by the zone that results in the highest PWM duty cycle value. Notes: Software can be alerted of an out-of-limit condition by the INT# pin if a status bit is set and enabled and the interrupt function is enabled on either the PWM2 or TACH3 pins Software can monitor the operation of the Fans through the Fan Tachometer Reading registers and by the PWM x Current PWM duty registers. It can also monitor current temperature readings through the Temperature Limit Registers if hardware monitoring is enabled. Fan control in auto mode is implemented without any input from external processor. In auto "Zone" mode, the speed is adjusted automatically as shown in the following figure. Fans are assigned to a zone(s). It is possible to have more than one fan assigned to a thermal zone or to have multiple zones assigned to one fan. Figure 7.2 on page 34 shows the control for the auto fan algorithm. The part allows a minimum temperature to be set, below which the fan will run at minimum speed. A temperature range is specified over which the part will automatically adjust the fan speed. If the minimum fan speed is set to 00h, then, when the temperature exceeds the low limit, the fan will "spin up" by going on full for a programmable amount of time. Following this spin up time, the fan will go to a duty cycle computed by the auto fan algorithm. As the temperature rises, the duty cycle will increase until the fan is running at full-speed when the temperature reaches the minimum plus the range value. The effect of this is a temperature feedback loop, which will cause the temperature to reach equilibrium between the minimum temperature and the minimum temperature plus the range. Provided that the fan has adequate cooling capacity for all environmental and power dissipation conditions, this system will maintain the temperature within acceptable limits, while allowing the fan to run slower (and quieter) when less cooling is required.
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Temp TMAX = TMIN + TRANGE
PWM Min set to 0%
Temp TMAX = TMIN + TRANGE
PWM Min set to x% (x is not 0)
TMIN
TMIN
Duty Cycle 100%
Duty Cycle 100%
Min
spin-up time Note: When spin-up ends, the PWM is set to the current calculated PWM
Figure 7.2 Automatic Fan Control
7.1.3.3
Spin Up
When a fan is being started from a stationary state (PWM duty cycle =00h), the part will cause the fan to "spin up" by going to 100% duty cycle for a programmable amount of time to overcome the inertia of the fan (i.e., to get the fan turning). Following this spin up time, the fan will go to the duty cycle computed by the auto fan algorithm. Note 7.3 The EMC2300 automatically performs the Spin Up routine upon power-up. The only conditions that will allow the fan to be in an stationary state are if the user programs the PWM input to 00h (in Manual Mode) or the user programs the Minimum PWM to 00h and the corresponding temperature channel(s) are below the low temperature limit.
During spin-up, the PWM duty cycle is reported as 0%. To limit the spin-up time and thereby reduce fan noise, the part uses feedback from the tachometers to determine when each fan has started spinning properly. The following tachometer feedback is included into the auto fan algorithm during spin-up. Auto Fan operation during Spin Up: The PWM goes to 100% duty cycle until the tachometer reading register is below the minimum limit (see Figure 7.4), or the spin-up time expires, whichever comes first. This causes spin-up to continue until the tachometer enters the valid count range, unless the spin up time expires. If the spin up expires before the tachometer enters the valid range, an interrupt status bit will be set once spin-up expires. Note that more than one tachometer may be associated with a PWM, in which case all tachometers associated with a PWM must be in the valid range for spin-up to end.
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PWM Output
duty cycle = 0%
duty cycle = 100%
tach reading vs. tach limit
FFFFh
tach reading > tach limit
tach reading < tach limit
Spin Up Time Programmed Spin Up Time
Note: When Spin Up Reduction is enabled (SUREN), the Spin Up time will be less than or equal to the programmed time for Spin Up. Once the tachometer(s) associated with a PWM output are operating within the programmed limits or the Spin Up time expires, whichever comes first, the PWM output is reduced to the calculated duty cycle.
Figure 7.4 Spin Up Reduction Enabled This feature defaults to enabled; it can be disabled by clearing bit 4 of the Configuration register (7Fh). If disabled, the all fans go to 100% duty cycle for the duration of their associated spin up time. Note that the Tachometer x minimum registers must be programmed to a value less than FFFFh in order for the spin up reduction to work properly. Notes: The tachometer reading register always gives the actual reading of the tachometer input. No interrupt bits are set during spin-up.
7.1.3.4
Hottest Option
If the "Hottest" option is chosen (101 or 110), then the fan is controlled by the limits and parameters associated with the zone that requires the highest PWM duty cycle value, as calculated by the auto fan algorithm.
7.1.3.5
Ramp Rate Control Logic
The Ramp Rate Control Logic, if enabled, limits the amount of change in the PWM duty cycle over a specified period of time. This period of time is programmable in the Ramp Rate Control registers located at offsets 62h and 63h.
7.1.3.5.1
RAMP RATE CONTROL DISABLED: (DEFAULT) The Auto Fan Control logic determines the duty cycle for a particular temperature. If PWM Ramp Rate Control is disabled, the PWM output will be set to this calculated duty cycle.
7.1.3.5.2
RAMP RATE CONTROL ENABLED: If PWM Ramp Rate Control is enabled, the PWM duty cycle will Ramp up or down to the new duty cycle computed by the auto fan control logic at the programmed Ramp Rate. The PWM Ramp Rate Control logic compares the current duty cycle computed by the auto fan logic with the previous ramp rate duty cycle. If the current duty cycle is greater than the previous ramp rate duty cycle the ramp rate duty cycle is incremented by `1' at the programmed ramp rate until it is greater than or equal to the current calculated duty cycle. If the current duty cycle is less than the previous ramp rate duty cycle, the ramp rate duty cycle is decremented by `1' until it is less than or equal to the current duty cycle. If the current PWM duty cycle is equal to the calculated duty cycle the PWM output will remain unchanged.
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Internally, the PWM Ramp Rate Control Logic will increment/decrement the internal PWM Duty cycle by `1' at a rate determined by the Ramp Rate Control Register (see Register 62h, 63h: PWM Ramp Rate Control on page 63). The actual duty cycle output is changed once per the period of the PWM output, which is determined by the frequency of the PWM output. (See Figure 7.6 Illustration of PWM Ramp Rate Control on page 37.) If the period of the PWM output is less than the step size created by the PWM Ramp Rate, the PWM output will hold the duty cycle constant until the Ramp Rate logic increments/decrements the duty cycle by `1' again. For example, if the PWM frequency is 87.7Hz (1/87.7Hz = 11.4msec) and the PWM Step time is 206msec, the PWM duty cycle will be held constant for a minimum of 18 periods (206/11.4 = 18.07) until the Ramp Logic increments/decrements the actual PWM duty cycle by `1'. If the period of the PWM output is greater than the step size created by the PWM Ramp Rate, the ramp rate logic will force the PWM output to increment/decrement the actual duty cycle in increments larger than 1/255. For example, if the PWM frequency is 11Hz (1/11Hz = 90.9msec) and the PWM Step time is 5msec, the PWM duty cycle output will be incremented 18 or 19 out of 255 (i.e., 90.9/5 = 18.18) until it reaches the calculated duty cycle. Notes: The step size may be less if the calculated duty cycle minus the actual duty cycle is less than 18. The calculated PWM Duty cycle reacts immediately to a change in the temperature reading value. The temperature reading value may be updated once in 624msec, once in 78msec, once in 223msec (default), or once in 447msec (see Table 6.2, "Conversion Cycle Timing," on page 21). The internal PWM duty cycle generated by the Ramp Rate control logic gradually ramps up/down to the calculated duty cycle at a rate pre-determined by the value programmed in the PWM Ramp Rate Control bits . The PWM output latches the internal duty cycle generated by the Ramp Rate Control Block every 1/(PWM frequency) seconds to determine the actual duty cycle of the PWM output pin. PWM Output Transition from OFF to ON When the calculated PWM Duty cycle generated by the auto fan control logic transitions from the `OFF' state to the `ON' state (i.e., Current PWM duty cycle>00h), the internal PWM duty cycle in the Ramp Rate Control Logic is initialized to the calculated duty cycle without any ramp time and the PWMx Current Duty Cycle register is set to this value.The PWM output will latch the current duty cycle value in the Ramp Rate Control block to control the PWM output. Note 7.5 This event will only occur if the MInimum PWM for a particular PWM driver is programmed to be 00h and is either changed (if the PWM driver is configured for Manual Operating Mode) or the temperature rises above the low limit (if the PWM driver is configured for Automatic Operating Mode).
PWM Output Transition from ON to OFF Each PWM output has a control bit to determine if the PWM output will transition immediately to the OFF state (default) or if it will gradually step down to Off at the programmed Ramp Rate. These control bits (SZEN) are located in the PWMx Options registers at offsets 94h-96h. This transition will only occur in Manual Mode if the user sets the PWM duty cycle to 0% from a nonzero value. Table 7.1 PWM Ramp Rate TIME PER PWM STEP (PWM STEP SIZE = 1/255) 206 msec
RRX-[2:0] 000
PWM RAMP TIME (SEC) (TIME FROM 33% DUTY CYCLE TO 100% DUTY CYCLE) 35
PWM RAMP TIME (SEC) (TIME FROM MIN DUTY CYCLE TO 100% DUTY CYCLE) 52.53
PWM RAMP RATE (HZ) 4.85
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Table 7.1 PWM Ramp Rate (continued) TIME PER PWM STEP (PWM STEP SIZE = 1/255) 104 msec 69 msec 41 msec 26 msec 18 msec 10 msec 5 msec
RRX-[2:0] 001 010 011 100 101 110 111
PWM RAMP TIME (SEC) (TIME FROM 33% DUTY CYCLE TO 100% DUTY CYCLE) 17.6 11.8 7.0 4.4 3.0 1.6 0.8
PWM RAMP TIME (SEC) (TIME FROM MIN DUTY CYCLE TO 100% DUTY CYCLE) 26.52 17.595 10.455 6.63 4.59 2.55 1.275
PWM RAMP RATE (HZ) 9.62 14.49 24.39 38.46 55.56 100 200
Example 1: PWM period < Ramp Rate Step Size PWM frequency = 87.7Hz (11.4msec) & PWM Ramp Rate = 38.46Hz (26msec)
Calculate Duty Cycle
70h 70h 71h
26ms
74h 72h
26ms
Ramping Duty Cycle
73h
26ms
74h
26ms
PWM Duty Cycle
70h
71h
11.4ms
71h
11.4ms
71h
11.4ms
72h
11.4ms
72h
11.4ms
73h
11.4ms
73h
11.4ms
73h
11.4ms
74h
11.4ms
74h
11.4ms
74h
Example 2: PWM period > Ramp Rate Step Size PWM frequency = 11Hz (90.9msec) & PWM Ramp Rate = 38.46Hz (26msec)
Calculate Duty Cycle
70h 70h 71h
26ms
74h 72h
26ms
Ramping Duty Cycle
73h
26ms
74h
26ms
PWM Duty Cycle
70h
71h
90.9msec
74h
Figure 7.6 Illustration of PWM Ramp Rate Control Notes: The PWM Duty Cycle latches the Ramping Duty Cycle on the rising edge of the PWM output. The calculated duty cycle, ramping duty cycle, and the PWM output duty cycle are asynchronous to each other, but are all synchronized to the internal 90kHz clock source.
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It should be noted that the actual duty cycle on the pin is created by the PWM Ramp Rate Control block and latched on the rising edge of the PWM output. Therefore, the current PWM duty cycle may lag the PWM Calculated Duty Cycle.
7.1.4
Fan Speed Monitoring
The chip monitors the speed of the fans by utilizing fan tachometer input signals from fans equipped with tachometer outputs. The fan tachometer inputs are monitored by using the Fan Tachometer registers. These signals, as well as the Fan Tachometer registers, are described below. The tachometers will operate in one of two modes: Mode 1: Standard tachometer reading mode. This mode is used when the fan is always powered. Mode 2: Enhanced tachometer reading mode. This mode is used when the PWM is pulsing the fan.
7.1.4.1
TACH Inputs
The tachometer inputs are implemented as digital input buffers with logic to filter out small glitches on the tach signal.
7.1.4.2
Selecting the Mode of Operation:
The mode is selected through the Mode Select bits located in the Tach Option register. This Mode Select bit is defined as follows: 0=Mode 1: Standard tachometer reading mode 1=Mode 2 (default): Enhanced tachometer reading mode. Default Mode of Operation: Mode 2 Slow interrupt disabled (Force FFFEh) Tach interrupt enabled via enable bit Tach Limit = FFFFh Look for 5 tach edges Don't ignore first 3 edges after guard time Guard Time = 32 clock periods (1 clock period = 1/90kHz). Tach readings updated once a second
7.1.4.3
Mode 1 - Always Monitoring
Mode 1 is the simple case. In this mode, the fan is always powered when it is `ON' and the fan tachometer output ALWAYS has a valid output. This mode is typically used if a linear DC Voltage control circuit drives the fan. In this mode, the fan tachometer simply counts the number of 90kHz pulses between the programmed number of edges (default = 5 edges). The fan tachometer reading registers are continuously updated. Notes: Some enhanced features added to support Mode 2, are available to Mode 1 also. They are: programmable number of tach edges and force tach reading register to FFFEh to indicate a SLOW fan. Five edges or two tach pulses are generated per revolution. The counter is used to determine the period of the Fan Tachometer input pulse. The counter starts counting on the first edge and continues counting until it detects the last edge or until it reaches FFFFh. If the programmed number of edges is detected on or before the counter reaches FFFFh, the reading register is updated with that count value. If the counter reaches FFFFh and no edges were detected
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a stalled fan event has occurred and the Tach Reading register will be set to FFFFh. If one or more edges are detected, but less than the programmed number of edges, a slow fan event has occurred and the Tach Reading register will be set to either FFFEh or FFFFh depending on the state of the Slow Tach bits located in the TACHx Options registers at offsets 90h - 93h. Software can easily compute the RPM value using the tachometer reading value if it knows the number of edges per revolution.
7.1.4.4
Mode 2 - Monitor Tach input When PWM is `ON'
In this mode, the PWM is used to pulse the Fan motor of a 3-wire fan. 3-wire fans use the same power supply to drive the fan motor and to drive the tachometer output logic. When the PWM is `ON' the fan generates valid tach pulses. When the PWM is not driving the Fan, the tachometer signal is not generated and the tach signal becomes indeterminate or tristate. Therefore, Mode 2 only makes tachometer measurements when the associated PWM is driving high during an update cycle. As a result, the Fan tachometer measurement is "synchronized" to the PWM output, such that it only looks for tach pulses when the PWM is `ON'. Notes: High frequency PWM operation is designed for use with four wire fans. Although some three wire fans are capable of operating with high frequency PWM, the tach output is very difficult to read. External circuitry is required for accurate tach reading of a three wire fan that is driven with high frequency PWM. Any fan tachometer input may be associated with any PWM output (see Linking Fan Tachometers to PWMs on page 44.)
7.1.4.4.1
ASSUMPTIONS (REFER TO FIGURE 7.7, "PWM AND TACHOMETER CONCEPT"): The Tachometer pulse generates 5 transitions per fan revolution (i.e., two fan tachometer periods per revolution, edges 26). One half of a revolution (one tachometer period) is equivalent to three edges (24 or 35). One quarter of a revolution (one-half tachometer period) is equivalent to two edges. To obtain the fan speed, count the number of 90Khz pulses that occurs between 2 edges i.e., 23, between 3 edges i.e., 24, or between 5 edges, i.e. 26 (the case of 9 edges is not shown). The time from 1-2 occurs through the guard time and is not to be used. For the discussion below, an edge is a high-to-low or low-to-high transition (edges are numbered - refer to Figure 7.7, "PWM and Tachometer Concept"). The Tachometer circuit begins monitoring the tach when the associated PWM output transitions high and the guard time has expired. Each tach circuit will continue monitoring until the programmed number of edges has been detected, whichever comes first. The Fan Tachometer value may be updated every 300ms, 500ms, or 1000ms.
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Internal PWM Signal
Guard time A Window for Valid Tach Pulses
PWM "ON"
1
Tach Pulses
2
3
4
5
6
Tach Pulses
A
B
C
D
E
F
Figure 7.7 PWM and Tachometer Concept 7.1.4.4.2 FAN TACHOMETER OPTIONS FOR MODE 2 2, 3, 5 or 9 "edges" to calculate the fan speed (Figure 7.7) Guard time A is programmable (8-63 clocks) to account for delays in the system (Figure 7.7) The PWM frequencies for modes 1 & 2 are: 11.0 Hz, 14.6 Hz, 21.9 Hz, 29.3 Hz, 35.2 Hz, 44.0 Hz, 58.6 Hz, 87.7Hz and 25Khz Option to ignore first 3 tachometer edges after guard time Option to force tach reading register to FFFEh to indicate a slow fan.
7.1.4.5
Fan Tachometer Reading Registers:
The Tachometer Reading registers are 16 bits, unsigned. When one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. The order is LSB first, MSB second. The value FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could be triggered by a counter overflow). These registers are read only - a write to these registers has no effect. Notes: The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional. FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This could be triggered by a counter overflow). The Tachometer registers are read only - a write to these registers has no effect. Mode 1 should be enabled and the tachometer limit register should be set to FFFFh if a tachometer input is left unconnected.
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Datasheet
7.1.4.6
Programming Options for Each Tachometer Input
The features defined in this section are programmable via the TACHx Option registers located at offsets 90h-93h and the PWMx Option registers located at offsets 94h-96h.
7.1.4.6.1
TACH READING UPDATE TIME In Mode 1, the Fan Tachometer Reading registers are continuously updated. In Mode 2, the fan tachometer registers are updated every 300ms, 500msec, or 1000msec. This option is programmed via bits[1:0] in the PWMx Option register. The PWM associated with a particular TACH(s) determines the TACH update time.
7.1.4.6.2
PROGRAMMED NUMBER OF TACH EDGES In modes 1 & 2, the number of edges is programmable for 2, 3, 5 or 9 edges (i.e., 1/2 tachometer pulse, 1 tachometer pulse, 2 tachometer pulses, 4 tachometer pulses). This option is programmed via bits[2:1] in the TachX Option register. Note: The "5 edges" case corresponds to two tachometer pulses, or 1 RPM for most fans. Using the other edge options will require software to scale the values in the reading register to correspond to the count for 1 RPM.
7.1.4.6.3
GUARD TIME (MODE 2 ONLY) The guard time is programmable from 8 to 63 clocks (90kHz). This option is programmed via bits[4:3] in the TachX Option register.
7.1.4.6.4
IGNORE FIRST 3 TACHOMETER EDGES (MODE 2 ONLY) Option to ignore first 3 tachometer edges after guard time. This option is programmed for each tachometer via bits[2:0] in the TACHx Option register. Default is do not ignore first 3 tachometer edges after guard time.
7.1.4.7
Summary of Operation for Modes 1 & 2
The following summarizes the detection cases: No edge occurs during the PWM `ON' time: indicate this condition as a stalled fan -The tachometer reading register contains FFFFh. One edge (or less than programmed number of edges) occurs during the PWM `ON' time : indicate this condition as a slow fan. -If the SLOW bit is set to 0, the tachometer reading register will be set to FFFEh to indicate that this is a slow fan instead of a seized fan. Note: This operation also pertains to the case where the tachometer counter reaches FFFFh before the programmed number of edges occurs. -If the SLOW bit is set to one, the tachometer reading register will be set to FFFFh. In this case, no distinction is made between a slow or seized fan. Note: The Slow Interrupt feature (SLOW) is configured in the TACHx Options registers at offsets 90h to 93h. The programmed number of edges occurs: -Mode 1: If the programmed number of edges occurs before the counter reaches FFFFh latch the tachometer count -Mode 2: If the programmed number of edges occurs during the PWM `ON' time: latch the tachometer count. (see Note below). Notes: Whenever the programmed number of edges is detected, the edge detection ends and the state machine is reset. The tachometer reading register is updated with the tachometer count value at this time. See Note 7.8 below for the one exception to this behavior.
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Note 7.8
This max value will be FFFFh if the programmed number of edges is detected when the count reaches FFFFh or if no edges are detected. If the count reaches FFFFh in Mode 1 and some edges were detected, but less than the programmed number of edges, the maximum tach count value is determined by the Slow Interrupt Enable bit located in the TACHx Options registers at offsets 90h to 93h. If slow interrupt detection is set to 0, the count will be forced to FFFEh, else the count will be forced to FFFFh.
7.1.4.8
Examples of Minimum RPMs Supported
The following tables show minimum RPMs that can be supported with the different parameters. The first table uses 3 edges and the second table uses 2 edges. As described in Assumptions (refer to Figure 7.7, "PWM and Tachometer Concept"): on page 39, the TACH detection circuitry expects a fan to deliver 5 TACH edges per full revolution. When measuring the fan speed using a PWM drive, the slowest fan speed that can be measured is dependent upon how long the PWM drive is high as well as how many edges are being counted to make a valid measurement. The data shown in Table 7.2 is taken by measuring 3 TACH edges or 1/2 of a single rotation. If the TACH signal is seen as a square wave with a fixed duty cycle and variable period (where period is inversely proportional to the fan speed), then 3 edges would coincide with a single TACH pulse. Therefore, in order to accurately measure a TACH signal using 3 edges, the PWM must be high for at least as long as the full period of the TACH signal. For example, if the PWM frequency is 87.7Hz (1st row), then the maximum measurement time available is 11.36msec at 100% duty cycle. This implies, that the maximum period that can be measured is also 11.36msec. Because period is inversely proportional to fan speed and 1 full period is equivalent to 1/2 a single rotation, this means that the minimum fan speed that can be detected at 100% duty cycle is:
1 - ----------------------- x 1 rotation x 1000ms x --------- = 2641 --------------------- 60s 11.36ms 2 s min The values shown in Table 7.2 and Table 7.3 include a guard time that occurs immediately after the PWM is set high where the TACH pulse is not measured. The effect of this guard time is to reduce the effective "on" time of the PWM with respect to measuring a TACH pulse. Table 7.2 Minimum RPM Detectable Using 3 Edges PWM FREQUENCY PULSE WIDTH AT DUTY CYCLE (PWM "ON" TIME) 100% (MSEC) (Note 7.9) 11.36 17 22.64 28.3 34 45.48 68.23 90.55
42
MINIMUM RPM AT DUTY CYCLE (Note 7.10) (30/TTachPulse)
(HZ) 87.7 58.6 44 35.2 29.3 21.9 14.6 11
25% (MSEC) 2.85 4.27 5.68 7.1 8.53 11.42 17.12 22.73
50% (MSEC) 5.7 8.53 11.36 14.2 17.06 22.83 34.25 45.45
25% 10865 7175 5366 4279 3554 2648 1761 1325
50% 5347 3554 2662 2126 1768 1319 878 661
100% 2662 1774 1330 1063 885 661 440 332
SMSC EMC2300
Revision 0.2 (06-14-06)
DATASHEET
Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
Note 7.9
100% duty cycle is 255/256.
Note 7.10 RPM=60/TRevolution, TTachPulse= TRevolution/2. Using 3 edges for detection, TTachPulse = (PWM "ON" Time - Guard Time). Minimum RPM values shown use minimum guard time (88.88usec). Table 7.3 Minimum RPM Detectable Using 2 Edges PWM FREQUENCY PULSE WIDTH AT DUTY CYCLE (PWM "ON" TIME) 100% (MSEC) (Note 7.11) 11.36 17 22.64 28.3 34 45.48 68.23 90.55 MINIMUM RPM AT DUTY CYCLE (Note 7.12) (30/TTachPulse)
(HZ) 87.7 58.6 44 35.2 29.3 21.9 14.6 11
25% (MSEC) 2.85 4.27 5.68 7.1 8.53 11.42 17.12 22.73
50% (MSEC) 5.7 8.53 11.36 14.2 17.06 22.83 34.25 45.45
25% 5433 3588 2683 2139 1777 1324 881 663
50% 2673 1777 1331 1063 884 660 439 331
100% 1331 887 665 532 442 330 220 166
Note 7.11 100% duty cycle is 255/256 Note 7.12 RPM=60/TRevolution, TTachPulse= TRevolution/2. Using 2 edges for detection, TTachPulse = 2*(PWM "ON" Time-Guard Time). Minimum RPM values shown use minimum guard time (88.88usec).
7.1.4.9
Detection of a Stalled Fan
There is a fan failure bit (TACHx) in the interrupt status register used to indicate that a slow or stalled fan event has occurred. If the tach reading value exceeds the value programmed in the tach limit register the interrupt status bit is set. See Interrupt Status register 2 at offset 42h. Notes: The reading register will be forced to FFFFh if a stalled event occurs (i.e., stalled event =no edges detected.) The reading register will be forced to either FFFFh or FFFEh if a slow fan event occurs. (i.e., slow event: 0 < #edges < programmed #edges). If the control bit, SLOW, located in the TACHx Options registers at offsets 90h - 93h, is set then FFFEh will be forced into the corresponding Tach Reading Register to indicate that the fan is spinning slowly. The fan tachometer reading register stays at FFFFh in the event of a stalled fan. If the fan begins to spin again, the tachometer logic will reset and latch the next valid reading into the tachometer reading register.
7.1.4.10
Fan Interrupt Status Bits
The status bits for the fan events are in Interrupt Status Register 2 (42h). These bits are set when the reading register is above the tachometer minimum and the Interrupt Enable 2 (Fan Tachs) register bits are configured to enable Fan Tach events. No interrupt status bits are set for fan events (even if the fan is stalled) if the associated tachometer minimum is set to FFFFh (registers 54h-5Bh).
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Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
Note: The Interrupt Enable 2 (Fan Tachs) register at offset 80h defaults to enabled for the individual tachometer status events bits. The group Fan Tach INT# bit defaults to disabled. This bit needs to be set if Fan Tach interrupts are to be generated on the external INT# pin. See Figure 6.3 Interrupt Control on page 24.
7.1.5
Linking Fan Tachometers to PWMs
The TACH/PWM Association Register at offset 81h is used to associate a Tachometer input with a PWM output. This association has three purposes: 1. The auto fan control logic supports a feature called SpinUp Reduction. If SpinUp Reduction is enabled (SUREN bit), the auto fan control logic will stop driving the PWM output high if the associated TACH input is operating within normal parameters. (Note: SUREN bit is located in the Configuration Register at offset 7Fh) 2. To measure the tachometer input in Mode 2, the tachometer logic must know when the associated PWM is `ON'. 3. Inhibit fan tachometer interrupts when the associated PWM is `OFF'. See the description of the PWM_TACH register. The default configuration is: PWM1 -> TACH1. PWM2 -> TACH2. PWM3 -> TACH3 & TACH4.
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Definition for the Lock and Start columns: Yes = Register is made read-only when the related bit is set; No = Register is not made read-only when the related bit is set. Table 8.1 Register Summary
Reg Addr Read /Write Reg Name Bit 7 MSb Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSb Default Value Lock Start
20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 3Eh 3Fh 40h
R R R R R R R R R R R R R R R R R/W Note 8.1 R/W Note 8.1 R/W Note 8.1 R R R/W Note 8.2
Reserved Vccp Reading VCC Reading Reserved Reserved Remote Diode 1 Temp Reading Internal Temp Reading Remote Diode 2 Temp Reading Tach1 LSB Tach1 MSB Tach2 LSB Tach2 MSB Tach3 LSB Tach3 MSB Tach4 LSB Tach4 MSB PWM1 Current Duty Cycle PWM2 Current Duty Cycle PWM3 Current Duty Cycle Company ID Version / Stepping Ready/Lock/Start
RES 7 7 RES RES 7 7 7 7 15 7 15 7 15 7 15 7 7 7 7 VER3 RES
RES 6 6 RES RES 6 6 6 6 14 6 14 6 14 6 14 6 6 6 6 VER2 RES
RES 5 5 RES RES 5 5 5 5 13 5 13 5 13 5 13 5 5 5 5 VER1 RES
RES 4 4 RES RES 4 4 4 4 12 4 12 4 12 4 12 4 4 4 4 VER0 RES
RES 3 3 RES RES 3 3 3 3 11 3 11 3 11 3 11 3 3 3 3 STP3 OVRID
RES 2 2 RES RES 2 2 2 2 10 2 10 2 10 2 10 2 2 2 2 STP2 READY
RES 1 1 RES RES 1 1 1 1 9 1 9 1 9 1 9 1 1 1 1 STP1 LOCK
RES 0 0 RES RES 0 0 0 0 8 0 8 0 8 0 8 0 0 0 0 STP0 START
00h N/A N/A 00h 00h N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 5Ch 6Ah 00h
No No No No No No No No No No No No No No No No Yes Note 8.1 Yes Note 8.1 Yes Note 8.1 No No Yes Note 8.2
No No No No No No No No No No No No No No No No No No No No No
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Chapter 8 Register Set
Table 8.1 Register Summary (continued)
Reg Addr Read /Write Reg Name Bit 7 MSb Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSb Default Value Lock Start
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Datasheet
Fan Control Device with High Frequency PWM and Temperature Monitors
41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh
R-C Note 8.3 R-C Note 8.3 R R R R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Interrupt Status Register 1 Interrupt Status Register 2 Reserved Reserved Reserved Vccp Low Limit Vccp High Limit VCC Low Limit VCC High Limit Reserved Reserved Reserved Reserved Remote Diode 1 Low Temp Remote Diode 1 High Temp Internal Low Temp Internal High Temp Remote Diode 2 Low Temp Remote Diode 2 High Temp Tach1 Minimum LSB Tach1 Minimum MSB Tach2 Minimum LSB Tach2 Minimum MSB Tach3 Minimum LSB Tach3 Minimum MSB Tach4 Minimum LSB Tach4 Minimum MSB PWM 1 Configuration PWM 2 Configuration PWM 3 Configuration Zone 1 Range/PWM 1 Frequency
INT2 ERR2 RES RES RES 7 7 7 7 RES RES RES RES 7 7 7 7 7 7 7 15 7 15 7 15 7 15 ZON2 ZON2 ZON2 RAN3
D2 ERR1 RES RES RES 6 6 6 6 RES RES RES RES 6 6 6 6 6 6 6 14 6 14 6 14 6 14 ZON1 ZON1 ZON1 RAN2
AMB TACH4 RES RES RES 5 5 5 5 RES RES RES RES 5 5 5 5 5 5 5 13 5 13 5 13 5 13 ZON0 ZON0 ZON0 RAN1
D1 TACH3 RES RES RES 4 4 4 4 RES RES RES RES 4 4 4 4 4 4 4 12 4 12 4 12 4 12 INV INV INV RAN0
RES TACH2 RES RES RES 3 3 3 3 RES RES RES RES 3 3 3 3 3 3 3 11 3 11 3 11 3 11 RES RES RES FRQ3
VCC TACH1 RES RES RES 2 2 2 2 RES RES RES RES 2 2 2 2 2 2 2 10 2 10 2 10 2 10 SPIN2 SPIN2 SPIN2 FRQ2
Vccp RES RES RES RES 1 1 1 1 RES RES RES RES 1 1 1 1 1 1 1 9 1 9 1 9 1 9 SPIN1 SPIN1 SPIN1 FRQ1
RES RES RES RES RES 0 0 0 0 RES RES RES RES 0 0 0 0 0 0 0 8 0 8 0 8 0 8 SPIN0 SPIN0 SPIN0 FRQ0
00h 00h
No No
No No
00h FFh 00h FFh 00h 00h 00h 00h 81h 7Fh 81h 7Fh 81h 7Fh FFh FFh FFh FFh FFh FFh FFh FFh 62h 62h 62h C3h
No No No No No No No No No No No No No No No No No No No No No No Yes Yes Yes Yes
No No No No No No No No No No No No No No No No No No No No No No No No No No
Reg Addr
Read /Write
Reg Name
Bit 7 MSb
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 LSb
Default Value
Lock
Start
60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Fh 7Ch 7Dh 7Eh 7Fh 80h 81h 82h 85h 86h 87h
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 8.4 R R/W R/W R/W R/W R/W R R R
Zone 2 Range/PWM 2 Frequency Zone 3 Range/PWM 3 Frequency PWM1 Ramp Rate Control PWM 2, PWM3 Ramp Rate Control PWM 1 MINIMUM Duty Cycle PWM 2 MINIMUM Duty Cycle PWM 3 MINIMUM Duty Cycle Zone 1 Low Temp Limit Zone 2 Low Temp Limit Zone 3 Low Temp Limit Zone 1 Temp Absolute Limit Zone 2 Temp Absolute Limit Zone 3 Temp Absolute Limit XOR Test Tree Enable Special Function Register Reserved Interrupt Enable 1 (Voltages) Configuration Interrupt Enable 2 (Fan Tachs) TACH_PWM Association Interrupt Enable 3 (Temp) A/D Converter LSbs Reg 1 A/D Converter LSbs Reg 2 A/D Converter LSbs Reg 3
RAN3 RAN3 RES RR2E 7 7 7 7 7 7 7 7 7 RES AVG2 RES VCC INIT RES T4H RES RD2.3 RES RES
RAN2 RAN2 RES RR2-2 6 6 6 6 6 6 6 6 6 RES AVG1 RES RES SMSC RES T4L RES RD2.2 RES RES
RAN1 RAN1 RES RR2-1 5 5 5 5 5 5 5 5 5 RES AVG0 RES RES SMSC RES T3H RES RD2.1 RES RES
RAN0 RAN0 RES RR2-0 4 4 4 4 4 4 4 4 4 RES SMSC RES RES SUREN TACH4 T3L RES RD2.0 RES RES
FRQ3 FRQ3 RR1E RR3E 3 3 3 3 3 3 3 3 3 RES SMSC RES VCCP TRDY TACH3 T2H D2EN RD1.3 AM.3 RES
FRQ2 FRQ2 RR1-2 RR3-2 2 2 2 2 2 2 2 2 2 RES INTEN RES RES RES TACH2 T2L D1EN RD1.2 AM.2 RES
FRQ1 FRQ1 RR1-1 RR3-1 1 1 1 1 1 1 1 1 1 RES MON-MD RES RES P2INT TACH1 T1H AMB RD1.1 AM.1 RES
FRQ0 FRQ0 RR1-0 RR3-0 0 0 0 0 0 0 0 0 0 XEN LPMD Note 8.5 RES VOLT T3INT TACH T1L TEMP RD1.0 AM.0 RES
C3h C3h E0h 00h 80h 80h 80h 80h 80h 80h 64h 64h 64h 00h 40h 00h ECh 10h 1Eh A4h 0Eh N/A N/A N/A
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Note 8.4 No Yes Yes Yes Yes Yes No No No
No No No No No No No No No No No No No No No No No No No No No No No
Note 8.7 Note 8.7
Note 8.7 Note 8.7
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Revision 0.2 (06-14-06)
Table 8.1 Register Summary (continued)
Table 8.1 Register Summary (continued)
Reg Addr Read /Write Reg Name Bit 7 MSb Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSb Default Value Lock Start
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Datasheet
Fan Control Device with High Frequency PWM and Temperature Monitors
88h 90h 91h 92h 93h 94h 95h 96h FFh
R R/W R/W R/W R/W R/W R/W R/W R
A/D Converter LSbs Reg 4 Tach1 Option Tach2 Option Tach3 Option Tach4 Option PWM1 Option PWM2 Option PWM3 Option SMSC Test Register
VCC.3 RES RES RES RES RES RES RES TST7
VCC.2 RES RES RES RE S RES RES RES TST 6
VCC.1 RES RES RES RES OPP OPP OPP TST 5
VCC.0 3EDG 3EDG 3EDG 3EDG GRD1 GRD1 GRD1 TST 4
VCP.3 MODE MODE MODE MODE GRD0 GRD0 GRD0 TST3
VCP.2 EDG1 EDG1 EDG1 EDG1 SZEN SZEN SZEN TST2
VCP.1 EDG0 EDG0 EDG0 EDG0 UPDT1 UPDT1 UPDT1 TST1
VCP.0 SLOW SLOW SLOW SLOW UPDT0 UPDT0 UPDT0 TST0
N/A 04h 04h 04h 04h 0Ch 0Ch 0Ch N/A
No No No No No Yes Yes Yes No
No No No No No No No No No
Note 8.6 Note 8.6 Note 8.6 Note 8.6 Note 8.6 Note 8.6
Note: SMSC Test Registers may be read/write registers. Writing these registers can cause unwanted results. Note 8.1 Note 8.2 Note 8.3 Note 8.4 Note 8.5 Note 8.6 Note 8.7 The PWMx Current Duty Cycle Registers are only writable when the associated fan is in manual mode. In this case, the register is writable when the start bit is set, but not when the lock bit is set. The Lock bit in the Ready/Lock/Start register is locked by the Lock Bit. The START and OVRID bits are always writable, both when the start bit is set and when the lock bit is set. The Interrupt status registers are cleared on a read if no events are active The INTEN bit in register 7Ch is always writable, both when the start bit is set and when the lock bit is set. In Shutdown Mode (LPMD=1 & START=0) all the H/W Monitoring registers/bits are not accessible except for the following: Bits[2:0] in the Special Function Register (SFTR) at offset 7Ch and Bits[7:0] in the Configuration register at offset 7Fh. These Reserved bits are read/write bits. Writing these bits to a `1' has no effect on the hardware. SMSC bits may be read/write bits. Writing these bits to a value other than the default value may cause unwanted results
Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
8.1
Undefined Registers
The registers shown in Table 8.1, "Register Summary" above are the defined registers in the part. Any reads to undefined registers always return 00h. Writes to undefined registers have no effect and do not return an error.
8.2
8.2.1
Defined Registers
Registers 20-24h: Voltage Reading
Table 8.2 Registers 20-24h: Voltage Reading
Register Address 21h 22h
Read/ Write R R
Register Name Vccp Reading VCC Reading
Bit 7 (MSb) 7 7
Bit 6 6 6
Bit 5 5 5
Bit 4 4 4
Bit 3 3 3
Bit 2 2 2
Bit 1 1 1
Bit 0 (LSb) 0 0
Default Value N/A N/A
The Voltage Reading registers reflect the current voltage of the EMC2300 voltage monitoring inputs. Voltages are presented in the registers at 3/4 full scale for the nominal voltage, meaning that at nominal voltage, each register will read C0h. Table 8.3 Voltage vs. Register Reading REGISTER READING AT NOMINAL VOLTAGE C0h C0h REGISTER READING AT MAXIMUM VOLTAGE FFh FFh REGISTER READING AT MINIMUM VOLTAGE 00h 00h
INPUT Vccp VCC
NOMINAL VOLTAGE 2.25V 3.3V
MAXIMUM VOLTAGE 3.00V 4.38V
MINIMUM VOLTAGE 0V 0V
The Voltage Reading registers will be updated automatically by the EMC2300 Chip with a minimum frequency of 4Hz. These registers are read only - a write to these registers has no effect.
8.2.2
Registers 25-27h: Temperature Reading
Table 8.4 Registers 25-27h: Temperature Reading
Register Address 25h 26h 27h
Read/ Write R R R
Register Name Remote Diode 1 Temp Reading Internal Temp Reading Remote Diode 2 Temp Reading
Bit 7 (MSb) 7 7 7
Bit 6 6 6 6
Bit 5 5 5 5
Bit 4 4 4 4
Bit 3 3 3 3
Bit 2 2 2 2
Bit 1 1 1 1
Bit 0 (LSb) 0 0 0
Default Value N/A N/A N/A
The Temperature Reading registers reflect the current temperatures of the internal and remote diodes. Remote Diode 1 Temp Reading register reports the temperature measured by the Remote1- and Remote1+ pins, Remote Diode 2 Temp Reading register reports the temperature measured by the Remote2- and Remote2+ pins, and the Internal Temp Reading register reports the temperature measured by the internal (ambient) temperature sensor. Current temperatures are represented as 8 bit, 2's complement, signed numbers in Celsius, as shown below in Table 8.5. The Temperature Reading register will return a value of 80h if the remote diode pins are not implemented by the board designer or are not functioning properly (this corresponds to the diode fault interrupt status bits). The
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Datasheet
Temperature Reading registers will be updated automatically by the EMC2300 Chip with a minimum frequency of 4Hz. Note: These registers are read only - a write to these registers has no effect. Each of the temperature reading registers are mapped to a zone. Each PWM may be programmed to operate in the auto fan control operating mode by associating a PWM with one or more zones. The following is a list of the zone associations. Zone 1 is controlled by Remote Diode 1 Temp Reading Zone 2 is controlled by Internal Temp Reading (Ambient Temperature Sensor) Zone 3 is controlled by Remote Diode 2 Temp Reading Table 8.5 Temperature vs. Register Reading TEMPERATURE -127c . . . -50c . . . 0c . . . 50c . . . 127c (SENSOR ERROR) READING (DEC) -127 . . . -50 . . . 0 . . . 50 . . . 127 READING (HEX) 81h . . . CEh . . . 00h . . . 32h . . . 7Fh 80h
8.2.3
Registers 28-2Fh: Fan Tachometer Reading
Table 8.6 Registers 28-2Fh: Fan Tachometer Reading
Register Address 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh
Read/ Write R R R R R R R R
Register Name Tach1 LSB Tach1 MSB Tach2 LSB Tach2 MSB Tach3 LSB Tach3 MSB Tach4 LSB Tach4 MSB
Bit 7 (MSb) 7 15 7 15 7 15 7 15
Bit 6 6 14 6 14 6 14 6 14
Bit 5 5 13 5 13 5 13 5 13
Bit 4 4 12 4 12 4 12 4 12
Bit 3 3 11 3 11 3 11 3 11
Bit 2 2 10 2 10 2 10 2 10
Bit 1 1 9 1 9 1 9 1 9
Bit 0 (LSb) 0 8 0 8 0 8 0 8
Default Value N/A N/A N/A N/A N/A N/A N/A N/A
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Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
The Fan Tachometer Reading registers contain the number of 11.111s periods (90KHz) between full fan revolutions. Fans produce two tachometer pulses per full revolution. These registers are updated at least once every second. To convert the value in the TACH reading registers to a representative RPM value is a simple mathematical exercise. The 16bit reading is first converted to a decimal number and then multiplied by the clock period (11.11s). This gives the measured period of two full TACH pulses which equals 1 full fan revolution. This number is then inverted and multiplied by 60 to give Rotations / minute. For example: If the Tach 1 data bytes contain 0C86h (MSB followed by LSB). This is equivalent to 3206 clock counts. Multiplying this number by 11.111s (clock period) yields 0.03562s. This number represents the measured time for two full periods of the TACH signal. Inverting this number and multiplying it by 60 yields a final RPM value of 1684. The larger the returned count, the slower the measured fan speed. The slowest fan speed that can be stored is approximately 82RPM with an output code of FFFDh. This slow speed is not practical to measure in TACH monitoring Mode 2 (see Table 7.2 on page 42 and Table 7.3 on page 43 for minimum RPM's measured using Mode 2 and Section 7.1.4.4, "Mode 2 - Monitor Tach input When PWM is `ON'," on page 39 for a description of this monitoring mode). This value is represented for each fan in a 16 bit, unsigned number. The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional, including when the start bit=0. When one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. The order is LSB first, MSB second. FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This could be triggered by a counter overflow). FFFEh, if the SLOW bit in the corresponding TACHx Option register is set (see Section 8.2.27, "Registers 90h-93h: TachX Option Registers," on page 72 for details), indicates that fan is spinning, but too slowly to be measured at the current TACH settings. These registers are read only - a write to these registers has no effect.
8.2.4
Registers 30-32h: Current PWM Duty
Table 8.7 Registers 30-32h: Current PWM Duty
Register Address 30h
Read/ Write R/W (See Note 8.8) R/W (See Note 8.8) R/W (See Note 8.8)
Register Name PWM1 Current Duty Cycle
Bit 7 (MSb) 7
Bit 6 6
Bit 5 5
Bit 4 4
Bit 3 3
Bit 2 2
Bit 1 1
Bit 0 (LSb) 0
Default Value N/A
31h
PWM2 Current Duty Cycle
7
6
5
4
3
2
1
0
N/A
32h
PWM3 Current Duty Cycle
7
6
5
4
3
2
1
0
N/A
Note 8.8
These registers are only writable when the associated fan is in manual mode. These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect.
The Current PWM Duty registers store the duty cycle that the chip is currently driving the PWM signals at. At initial power-on, the duty cycle is 100% and thus, when read, this register will return FFh. After the Ready/Lock/Start Register Start bit is set, this register and the PWM signals are updated based
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Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
on the algorithm described in the Auto Fan Control Operating Mode section and the Ramp Rate Control logic, unless the associated fan is in manual mode - see below. Note: When the device is configured for Manual Mode, the Ramp Rate Control logic should be disabled. When read, the Current PWM Duty registers return the current PWM duty cycle for the respective PWM signal. These registers are read only - a write to these registers has no effect. Note: If the current PWM duty cycle registers are written while the part is not in manual mode or when the start bit is zero, the data will be stored in internal registers that will only be active and observable when the start bit is set and the fan is configured for manual mode. While the part is not in manual mode and the start bit is zero, the current PWM duty cycle registers will read back FFh. Manual Mode (Test Mode) In manual mode, when the start bit is set to 1 and the lock bit is 0, the current duty cycle registers are writable to control the PWMs. Note: When the lock bit is set to 1, the current duty cycle registers are Read-Only. The PWM duty cycle is represented as follows: Table 8.8 PWM Duty vs Register Reading CURRENT DUTY 0%
... ...
VALUE (DECIMAL) 0
...
VALUE (HEX) 00h
25%
... ...
64
...
40h
50%
... ...
128
...
80h
100%
255
FFh
During spin-up, the PWM duty cycle is reported as 0%. Notes: The PWMx Current Duty Cycle always reflects the current duty cycle on the associated PWM pin. The PWMx Current Duty Cycle register is implemented as two separate registers: a read-only and a write-only. When a value is written to this register in manual mode there will be a delay before the programmed value can be read back by software. The hardware updates the read-only PWMx Current Duty Cycle register on the beginning of a PWM cycle. If Ramp Rate Control is disabled, the delay to read back the programmed value will be from 0 seconds to 1/(PWM frequency) seconds. Typically, the delay will be 1/(2*PWM frequency) seconds.
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Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
8.2.5
Register 3Eh: Company ID
Table 8.9 Register 3Eh: Company ID
Register Address 3Eh
Read/ Write R
Register Name Company ID
Bit 7 (MSb) 7
Bit 6 6
Bit 5 5
Bit 4 4
Bit 3 3
Bit 2 2
Bit 1 1
Bit 0 (LSb) 0
Default Value 5Ch
The Company ID register contains the company identification number. This number is a method for uniquely identifying the part manufacturer. This register is read only - a write to this register has no effect.
8.2.6
Register 3Fh: Version / Stepping
Table 8.10 Register 3Fh: Version / Stepping
Register Address 3Fh
Read/ Write R
Register Name Version / Stepping
Bit 7 (MSb) VER3
Bit 6 VER 2
Bit 5 VER 1
Bit 4 VER 0
Bit 3 STP 3
Bit 2 STP 2
Bit 1 STP 1
Bit 0 (LSb) STP0
Default Value 6Ah
The four least significant bits of the Version / Stepping register [3:0] contain the current stepping of the EMC2300 silicon. Stepping numbers are to begin from a value of 08h, to indicate that the register set is enhanced from previous hardware monitoring standards. The four most significant bits [7:4] reflect the version number, which will be fixed at 0110b. For the A0 stepping of this device, the register will read 01101000b. For the A1 stepping, this register will read 01101001b and so on. The register is used by application software to identify which device has been implemented in the given system. Based on this information, software can determine which registers to read from and write to. Further, application software may use the current stepping to implement work-arounds for bugs found in a specific silicon stepping. This register is read only - a write to this register has no effect.
8.2.7
Register 40h: Ready/Lock/Start Monitoring
Table 8.11 Register 40h: Ready/Lock/Start Monitoring
Register Address 40h
Read/ Write R/W
Register Name Ready/Lock/Start
Bit 7 (MSb) RES
Bit 6 RES
Bit 5 RES
Bit 4 RES
Bit 3 OVRID
Bit 2 READY
Bit 1 LOCK
Bit 0 (LSb) START
Default Value 00h
Setting the Lock bit makes the Lock bit read only.
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Table 8.12 Ready/Lock/Start Monitoring BIT 0 NAME START R/W R/W DEFAULT 0 DESCRIPTION When software writes a 1 to this bit, the EMC2300 enables monitoring and PWM output control functions based on the limit and parameter registers. Before this bit is set, the part does not update register values. Whenever this bit is set to 0, the monitoring and PWM output control functions are based on the default limits and parameters, regardless of the current values in the limit and parameter registers. The EMC2300 preserves the values currently stored in the limit and parameter registers when this bit is set or cleared. This bit is not affected by setting the Lock bit. Note: When this bit is 0, all fans are on full 100% duty cycle, i.e., PWM pins are high for 255 clocks, low for 1 clock. When this bit is 0, the part is not monitoring.
1
LOCK
R/W
0
Setting this bit to 1 locks specified limit and parameter registers. Once this bit is set, limit and parameter registers become read only and will remain locked until the device is powered off. This register bit becomes read only once it is set. The EMC2300 sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all A/D converters are functioning (all bias conditions for the A/Ds have stabilized and the A/Ds are in operational mode). (Always reads back `1'.) If this bit is set to 1, all PWM outputs go to 100% duty cycle regardless of whether or not the lock bit is set. Reserved.
2
READY
R
0
3 4-7
OVRID Reserved
R/W R
0 0
Note: There is a start-up time of up to 82ms for monitoring after the start bit is set to `1', during which time the reading registers are not valid. The following summarizes the operation of the part based on the Start bit: 1. If Start bit = '0' then: a. Fans are set to Full On. b. No voltage, temperature, or fan tach monitoring is performed. The values in the reading registers will be N/A (Not Applicable), which means these values will not be considered valid readings until the Start bit = '1'. The exception to this is the Tachometer reading registers, which always give the actual reading on the TACH pins. c. No Status bits are set. 2. If Start bit = '1' d. All fan control and monitoring will be based on the current values in the registers. There is no need to preserve the default values after software has programmed these registers because no monitoring or auto fan control will be done when Start bit = '0'. e. Status bits may be set. f. Setting the START bit to 1 does not prevent the limit and parameter registers from being written.
Note: Once programmed, the register values will be saved when start bit is reset to `0'.
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Fan Control Device with High Frequency PWM and Temperature Monitors
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8.2.8
Register 41h: Interrupt Status Register 1
Table 8.13 Register 41h: Interrupt Status Register 1
Register Address 41h
Read/ Write R-C (See Note 8.9)
Register Name Interrupt Status 1
Bit 7 (MSb) INT2
Bit 6 D2
Bit 5 AMB
Bit 4 D1
Bit 3 RES
Bit 2 VCC
Bit 1 Vccp
Bit 0 (LSb) RES
Default Value 00h
Note 8.9
This register is cleared on a read if no events are active.
Note: The individual enable bits for D2, AMB, and D1 are located in the Interrupt Enable 3 (Temp) register at offset 82h. The individual enable bits for, VCC, and Vccp, are located in the Interrupt Enable 1 register at offset 7Eh. The Interrupt Status Register 1 bits are automatically set by the device, if enabled, whenever the Vccp input voltage violate the limits set in the limit and parameter registers or when the measured temperature violates the limits set in the limit and parameter registers for any of the three thermal inputs. This register holds a bit set until the event is read by software or until the individual enable bit is cleared (see Note below). The contents of this register are cleared (set to 0) automatically by the EMC2300 after it is read by software, if the voltage or temperature no longer violates the limits set in the limit and parameter registers. Once set, the Interrupt Status Register 1 bits remain set until a read event occurs or until the individual enable bits is cleared, even if the voltage or temperature no longer violate the limits set in the limit and parameter registers. Note that clearing the group Temp, Fan, or Volt enable bits or the global INTEN enable bit has no effect on the status bits. See Registers 44-4Dh: Voltage Limit Registers on page 57 and on page 58. This register contains a bit that indicates that a bit is set in the other interrupt status register. If bit 7 is set, then a status bit is set in the Interrupt Status Register 2. Therefore, S/W can poll this register, and only if bit 7 is set does the other register need to be read. This bit is cleared (set to 0) automatically by the device if there are no bits set in Interrupt Status Registers 2. This register is read only - a write to this register has no effect. Note: Clearing the individual enable bits: 1. An interrupt status bit will never change from a 0 to a 1 when the corresponding individual interrupt enable bit is cleared (set to 0), regardless of whether the limits are violated during a measurement. 2. If the individual enable bit is cleared while the associated status bit is 1, the status bit will be cleared when the associated reading register is updated. The reading registers only get updated when the START bit is set to `1'. If the enable bit is cleared when the START bit is 0, the associated interrupt status bit will not be cleared until the start bit is set to 1 and the associated reading register is updated.
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Table 8.14 Interrupt Status Register 1
BIT 0 1 2 3 4 NAME Reserved Vccp_Error VCC_Error Reserved Remote Diode 1 Limit Error Internal Sensor Limit Error Remote Diode 2 Limit Error INT2 Event Active R/W R R R R R DEFAULT 0 0 0 0 0 Reserved The EMC2300 automatically sets this bit to 1 when the Vccp input voltage is less than or equal to the limit set in the Vccp Low Limit register or greater than the limit set in the Vccp High Limit register. The EMC2300 automatically sets this bit to 1 when the VCC input voltage is less than or equal to the limit set in the VCC Low Limit register or greater than the limit set in the VCC High Limit register. Reserved The EMC2300 automatically sets this bit to 1 when the temperature input measured by the Remote1- and Remote1+ is less than or equal to the limit set in the Remote Diode 1 Low Temp register or greater than the limit set in Remote Diode 1 High Temp register. The EMC2300 automatically sets this bit to 1 when the temperature input measured by the internal temperature sensor is less than or equal to the limit set in the Internal Low Temp register or greater than the limit set in the Internal High Temp register. The EMC2300 automatically sets this bit to 1 when the temperature input measured by the Remote2- and Remote2+ is less than or equal to the limit set in the Remote Diode 2 Low Temp register or greater than the limit set in the Remote Diode 1 High Temp register. The device automatically sets this bit to 1 when a status bit is set in the Interrupt Status Register 2. DESCRIPTION
5
R
0
6
R
0
7
R
0
8.2.9
Register 42h: Interrupt Status Register 2
Table 8.15 Register 42h: Interrupt Status Register 2
Register Address 42h
Read/ Write R-C (See Note 8.10)
Register Name Interrupt Status Register 2
Bit 7 (MSb) ERR2
Bit 6 ERR1
Bit 5 TACH4
Bit 4 TACH3
Bit 3 TACH2
Bit 2 TACH1
Bit 1 RES
Bit 0 (LSb) RES
Default Value 00h
Note 8.10 This register is cleared on a read if no events are active. This register is read only - a write to this register has no effect. The Interrupt Status Register 2 bits are automatically set by the device whenever a remote temperature sensor error occurs, or a tach reading value is above the minimum value set in the tachometer minimum registers. The Interrupt Status Register 2 register holds a set bit until the event is read by software or until the individual interrupt enable bit is cleared (see Note below). The contents of this register are cleared (set to 0) automatically by the EMC2300 after it is read by software,, if the temperature sensor error no loner exists, or if the tach reading register is no longer above the minimum. Once set, the Interrupt Status Register 2 bits remain set until a read event occurs or until the individual interrupt enable bit is cleared, even if the voltage, Tach, or diode event no longer exists. The remote diode fault bits do not clear on a read while the fault condition exists. If the start bit is set when a fault condition occurs, 80h will be loaded into the associated temperature reading register, which will cause the associated diode limit error bit to be set (Remote Diode 1 Limit Error or Remote Diode 2 Limit Error) in addition to the diode fault bit. Disabling the enable bit for the diode will clear both the fault bit and the error bit for that diode (see Note below). This register is read only - a write to this register has no effect.
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Fan Control Device with High Frequency PWM and Temperature Monitors
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Note: Clearing the individual enable bits. 1. An interrupt status bit will never change from a 0 to a 1 when the corresponding individual interrupt enable bit is cleared (set to 0), regardless of whether the limits are violated during a measurement. 2. If the individual enable bit is cleared while the associated status bit is 1, the status bit will be cleared when the associated reading register is updated. The reading registers only get updated when the START bit is set to `1'. If the enable bit is cleared when the START bit is 0, the associated interrupt status bit will not be cleared until the start bit is set to 1 and the associated reading register is updated.
Table 8.16 Interrupt Status Register 2
BIT 0 1 2 3 4 5 6 NAME Reserved Reserved TACH1 Slow/Stalled TACH2 Slow/Stalled TACH3 Slow/Stalled TACH4 Slow/Stalled Remote Diode 1 Fault R/W R R R R R R R DEFAULT 0 0 0 0 0 0 0 Reserved Reserved The EMC2300 automatically sets this bit to 1 when the TACH1 input reading is above the value set in the Tach1 Minimum MSB and LSB registers. The EMC2300 automatically sets this bit to 1 when the TACH2 input reading is above the value set in the Tach2 Minimum MSB and LSB registers. The EMC2300 automatically sets this bit to 1 when the TACH3 input reading is above the value set in the Tach3 Minimum MSB and LSB registers. The EMC2300 automatically sets this bit to 1 when the TACH4 input reading is above the value set in the Tach4 Minimum MSB and LSB registers. The EMC2300 automatically sets this bit to 1 when there is either a short or open circuit fault on the Remote1+ or Remote1- thermal diode input pins as defined in the section Diode Fault on page 24. Note: 7 Remote Diode 2 Fault R 0 If the START bit is set and a fault condition exists, the Remote Diode 1 reading register will be forced to 80h. DESCRIPTION
The EMC2300 automatically sets this bit to 1 when there is either a short or open circuit fault on the Remote2+ or Remote2- thermal diode input pins as defined in the section Diode Fault on page 24. Note: If the START bit is set and a fault condition exists, the Remote Diode 2 reading register will be forced to 80h.
8.2.10
Registers 44-4Dh: Voltage Limit Registers
Table 8.17 Registers 44-4Dh: Voltage Limit Registers
Register Address 46h 47h 48h 49h
Read/ Write R/W R/W R/W R/W
Register Name Vccp Low Limit Vccp High Limit VCC Low Limit VCC High Limit
Bit 7 (MSb) 7 7 7 7
Bit 6 6 6 6 6
Bit 5 5 5 5 5
Bit 4 4 4 4 4
Bit 3 3 3 3 3
Bit 2 2 2 2 2
Bit 1 1 1 1 1
Bit 0 (LSb) 0 0 0 0
Default Value 00h FFh 00h FFh
Setting the Lock bit has no effect on these registers. If a voltage input either exceeds the value set in the voltage high limit register or falls below or equals the value set in the voltage low limit register, the corresponding bit will be set automatically by the EMC2300 in the interrupt status registers (41-42h). Voltages are presented in the registers at 3/4 full scale for the nominal voltage, meaning that at nominal voltage, each input will be C0h, as shown in Table 8.18.
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Table 8.18 Voltage Limits vs. Register Setting
REGISTER SETTING AT NOMINAL VOLTAGE C0h C0h REGISTER SETTING AT MAXIMUM VOLTAGE FFh FFh REGISTER MINIMUM SETTING AT VOLTAGE MINIMUM VOLTAGE 0V 0V 00h 00h
NOMINAL INPUT VOLTAGE Vccp VCC 2.25V 3.3V
MAXIMUM VOLTAGE 3.00V 4.38V
8.2.11
Registers 4E-53h: Temperature Limit Registers
Table 8.19 Registers 4E-53h: Temperature Limit Registers
Register Address 4Eh 4Fh 50h 51h 52h 53h
Read/ Write R/W R/W R/W R/W R/W R/W
Register Name Remote Diode 1 Low Temp Remote Diode 1 High Temp Internal Low Temp Internal High Temp Remote Diode 2 Low Temp Remote Diode 2 High Temp
Bit 7 (MSb) 7 7 7 7 7 7
Bit 6 6 6 6 6 6 6
Bit 5 5 5 5 5 5 5
Bit 4 4 4 4 4 4 4
Bit 3 3 3 3 3 3 3
Bit 2 2 2 2 2 2 2
Bit 1 1 1 1 1 1 1
Bit 0 (LSb) 0 0 0 0 0 0
Default Value 81h 7Fh 81h 7Fh 81h 7Fh
Setting the Lock bit has no effect on these registers. If an external temperature input or the internal temperature sensor either exceeds the value set in the high limit register or is less than or equal to the value set in the low limit register, the corresponding bit will be set automatically by the EMC2300 in the Interrupt Status Register 1 (41h). For example, if the temperature reading from the Remote1- and Remote1+ inputs exceeds the Remote Diode 1 High Temp register limit setting, Bit[4] D1 of the Interrupt Status Register 1 will be set. The temperature limits in these registers are represented as 8 bit, 2's complement, signed numbers in Celsius, as shown below in Table 8.20. Table 8.20 Temperature Limits vs. Register Settings TEMPERATURE -127c . . . -50c . . . 0c . . . 50c . . . 127c
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LIMIT (DEC) -127 . . . -50 . . . 0 . . . 50 . . . 127
58
LIMIT (HEX) 81h . . . CEh . . . 00h . . . 32h . . . 7Fh
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8.2.12
Registers 54-5Bh: Fan Tachometer Low Limit
Table 8.21 Registers 54-5Bh: Fan Tachometer Low Limit
Register Address 54h 55h 56h 57h 58h 59h 5Ah 5Bh
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W
Register Name Tach1 Minimum LSB Tach1 Minimum MSB Tach2 Minimum LSB Tach2 Minimum MSB Tach3 Minimum LSB Tach3 Minimum MSB Tach4 Minimum LSB Tach4 Minimum MSB
Bit 7 (MSb) 7 15 7 15 7 15 7 15
Bit 6 6 14 6 14 6 14 6 14
Bit 5 5 13 5 13 5 13 5 13
Bit 4 4 12 4 12 4 12 4 12
Bit 3 3 11 3 11 3 11 3 11
Bit 2 2 10 2 10 2 10 2 10
Bit 1 1 9 1 9 1 9 1 9
Bit 0 (LSb) 0 8 0 8 0 8 0 8
Default Value FFh FFh FFh FFh FFh FFh FFh FFh
Setting the Lock bit has no effect on these registers. The Fan Tachometer Low Limit registers indicate the tachometer reading that, if exceeded, the corresponding bit will be set in the Interrupt Status Register 2 register. This register represents a number of clock counts between the programmed number of tach edges and therefore as the number increases, the effective RPM that it represents will decrease. The limit represents a fixed fan speed (though the TACH measurement options may limit fan speeds that can be measured). See Section 8.2.3 for a description of the TACH data formatting. In Auto Fan Control mode, the fan can run at high speeds (100% duty cycle), so care should be taken in software to ensure that the limit is low enough not to cause sporadic alerts. Note that an interrupt status event will be generated when the tachometer reading is greater than the minimum tachometer limit. The fan tachometer will not cause a bit to be set in the interrupt status register if the current value in the associated Current PWM Duty registers is 00h or if the PWM is disabled via the PWM Configuration Register. Interrupts will never be generated for a fan if its tachometer minimum is set to FFFFh.
8.2.13
Registers 5C-5Eh: PWM Configuration
Table 8.22 Registers 5C-5Eh: PWM Configuration
Register Address 5Ch 5Dh 5Eh
Read/ Write R/W R/W R/W
Register Name PWM 1 Configuration PWM 2 Configuration PWM 3 Configuration
Bit 7 (MSb) ZON2 ZON2 ZON2
Bit 6 ZON1 ZON1 ZON1
Bit 5 ZON0 ZON0 ZON0
Bit 4 INV INV INV
Bit 3 RES RES RES
Bit 2 SPIN2 SPIN2 SPIN2
Bit 1 SPIN1 SPIN1 SPIN1
Bit 0 (LSb) SPIN0 SPIN0 SPIN0
Default Value 62h 62h 62h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. Bits [7:5] Zone/Mode Bits [7:5] of the PWM Configuration registers associate each PWM with a temperature sensor.
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Fan Control Device with High Frequency PWM and Temperature Monitors
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When in Auto Fan Mode, the PWM will be assigned to a zone, and its PWM duty cycle will be adjusted according to the temperature of that zone. If `Hottest' option is selected (101 or 110), the PWM will be controlled by the hottest of zones 2 and 3, or of zones 1, 2, and 3. If one of these options is selected, the PWM is controlled by the limits and parameters for the zone that requires the highest PWM duty cycle, as computed by the auto fan algorithm. When in manual control mode, the PWMx Current Duty Cycle Registers (30h-32h) become Read/Write. It is then possible to control the PWM outputs with software by writing to these registers. See PWMx Current Duty Cycle Registers description. When the fan is disabled (100) the corresponding PWM output is driven low (or high, if inverted). When the fan is Full On (011) the corresponding PWM output is driven high (or low, if inverted). Notes: Zone 1 is controlled by Remote Diode 1 Temp Reading register Zone 2 is controlled by Internal Temp Reading Register Zone 3 is controlled by Remote Diode 2 Temp Reading register Table 8.23 Fan Zone Setting ZON[7:5] 000 001 010 011 100 101 110 111 Bit [4] PWM Invert Bit [4] inverts the PWM output. If set to 1, 100% duty cycle will yield an output that is low for 255 clocks and high for 1 clock. If set to 0, 100% duty cycle will yield an output that is high for 255 clocks and low for 1 clock. Bit [3] Reserved Bits [2:0] Spin Up Bits [2:0] specify the `spin up' time for the fan. When a fan is being started from a stationary state, the PWM output is held at 100% duty cycle for the time specified in Table 8.24, "Fan Spin-Up Register" before scaling to a lower speed. Note: during spin-up, the PWM pin is forced high for the duration of the spin-up time (i.e., 100% duty cycle = 256/256). Note: To reduce the spin-up time, this device has implemented a feature referred to as Spin Up Reduction. Spin Up Reduction uses feedback from the tachometers to determine when each fan has started spinning properly. Spin up for a PWM will end when the tachometer reading register is below the minimum limit, or the spin-up time expires, whichever comes first. All tachs associated with a PWM must be below min. for spin-up to end prematurely. This feature can be disabled by clearing bit 4 (SUREN) of the Configuration register (7Fh). If disabled, the all fans go on full for the duration of their associated spin up time. Note that the Tachx minimum registers must be programmed to a value less than FFFFh in order for the spin-up reduction to work properly. Fan on zone 1 auto Fan on zone 2 auto Fan on zone 3 auto Fan always on full Fan disabled Fan controlled by hottest of zones 2,3 Fan controlled by hottest of zones 1,2,3 Fan manually controlled PWM CONFIGURATION
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Fan Control Device with High Frequency PWM and Temperature Monitors
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Table 8.24 Fan Spin-Up Register SPIN[2:0] 000 001 010 011 100 101 110 111 SPIN UP TIME 0 sec 100ms 250ms (default) 400ms 700ms 1000ms 2000ms 4000ms
8.2.14
Registers 5F-61h: Zone Temperature Range, PWM Frequency
Table 8.25 Registers 5F-61h: Zone Temperature Range, PWM Frequency
Register Address 5Fh 60h 61h
Read/ Write R/W R/W R/W
Register Name Zone 1 Range / Fan 1 Frequency Zone 2 Range / Fan 2 Frequency Zone 3 Range / Fan 3 Frequency
Bit 7 (MSb) RAN3 RAN3 RAN3
Bit 6 RAN2 RAN2 RAN2
Bit 5 RAN1 RAN1 RAN1
Bit 4 RAN0 RAN0 RAN0
Bit 3 FRQ3 FRQ3 FRQ3
Bit 2 FRQ2 FRQ2 FRQ2
Bit 1 FRQ1 FRQ1 FRQ1
Bit 0 (LSb) FRQ0 FRQ0 FRQ0
Default Value C3h C3h C3h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. In Auto Fan Mode, when the temperature for a zone is above the Low Temperature Limit (registers 67-69h) and below the Absolute Temperature Limit (registers 6A-6Ch) the speed of a fan assigned to that zone is determined as follows by the auto fan control logic. When the temperature reaches the temperature value programmed in the Zone x Low Temp Limit register, the PWM output assigned to that zone is at PWMx Minimum Duty Cycle. Between Zone x Low Temp Limit and (Zone x Low Temp Limit + Zone x Range), the PWM duty cycle increases linearly according to the temperature as shown in the figure below.
PWM Duty is linear this range Below Fan Temp Limit: Fan at Fan PWM Minimum
Temperature
Temperature Low LIMIT: output at MIN FAN
Low LIMIT+ RANGE: Output at 100% Duty
Figure 8.11 Fan Activity Above Low Temp Limit
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Example for PWM1 assigned to Zone 1: Zone 1 Low Temp Limit (Register 67h) is set to 50C (32h). Zone 1 Range (Register 5Fh) is set to 8C (7h) PWM1 Minimum Duty Cycle (Register 64h) is set to 50% (80h) In this case, the PWM1 duty cycle will be 50% at 50C. Since (Zone 1 Low Temp Limit) + (Zone 1 Range) = 50C + 8C = 58C, the fan controlled by PWM1 will run at 100% duty cycle when the temperature of the Zone 1 sensor is at 58C. Since the midpoint of the fan control range is 54C, and the median duty cycle is 75% (Halfway between the PWM Minimum and 100%), PWM1 duty cycle would be 75% at 54C. Above (Zone 1 Low Temp Limit) + (Zone 1 Range), the duty cycle must be 100%. The PWM frequency bits [3:0] determine the PWM frequency for the fan. PWM Frequency Selection (Default =0011=29.3Hz) Table 8.26 Register Setting vs. PWM Frequency FREQ[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 - 1001 1010 1011 - 1111 Range Selection (Default =1100=32C) Table 8.27 Register Setting vs. Temperature Range RAN[3:0] 0000 0001 0010 0011 0100 0101 0110 RANGE (C) 2 2.5 3.33 4 5 6.67 8 PWM FREQUENCY 11.0 Hz 14.6 Hz 21.9 Hz 29.3 Hz (default) 35.2 Hz 44.0 Hz 58.6 Hz 87.7 Hz N/A ~25 Khz N/A
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Fan Control Device with High Frequency PWM and Temperature Monitors
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Table 8.27 Register Setting vs. Temperature Range (continued) RAN[3:0] 0111 1000 1001 1010 1011 1100 1101 1110 1111 RANGE (C) 10 13.33 16 20 26.67 32 40 53.33 80
Note: The range numbers will be used to calculate the slope of the PWM ramp up. For the fractional entries, the PWM will go on full when the temp reaches the next integer value e.g., for 3.33, PWM will be full on at (min. temp + 4).
8.2.15
Register 62h, 63h: PWM Ramp Rate Control
Table 8.28 Register 62h, 63h: Min/Off, PWM Ramp Rate Control
Register Address 62h 63h
Read/ Write R/W R/W
Register Name PWM 1 Ramp Rate Control PWM 2, PWM 3 Ramp Rate Control
Bit 7 (MSb) RES RR2E
Bit 6 RES RR2-2
Bit 5 RES RR2-1
Bit 4 RES RR2-0
Bit 3 RR1E RR3E
Bit 2 RR1-2 RR3-2
Bit 1 RR1-1 RR3-1
Bit 0 (LSb) RR1-0 RR3-0
Default Value E0h 00h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. The duty cycle will be set to the Minimum Fan Duty Cycle when the measured temperature falls below the Temperature LIMIT register setting for the corresponding PWM. Description of Ramp Rate Control bits: If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by the part. The auto fan control logic calculates the PWM duty cycle for all temperature readings. If Ramp Rate Control is disabled, the PWM output will jump or oscillate between different PWM duty cycles causing the fan to suddenly change speeds, which creates unwanted fan noise. If enabled, the PWM Ramp Rate Control logic will prevent the PWM output from jumping, instead the PWM will ramp up/down towards the new duty cycle at a pre-determined ramp rate. Ramp Rate Control The Ramp Rate Control logic limits the amount of change to the PWM duty cycle over a period of time. This period of time is programmable via the Ramp Rate Control bits. For a detailed description of the Ramp Rate Control bits see Table 8.29. For a description of the Ramp Rate Control logic see Ramp Rate Control Logic on page 35. Note: RR1E, RR2E, and RR3E enable PWM Ramp Rate Control for PWM 1, 2, and 3 respectively. RR1-2, RR1-1, and RR1-0 control ramp rate time for PWM 1 RR2-2, RR2-1, and RR2-0 control ramp rate time for PWM 2 RR3-2, RR3-1, and RR3-0 control ramp rate time for PWM 3
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Table 8.29 PWM Ramp Rate Control PWM RAMP TIME (SEC) (TIME FROM 33% DUTY CYCLE TO 100% DUTY CYCLE) 35 17.6 11.8 7.0 4.4 3.0 1.6 0.8 PWM RAMP TIME (SEC) (TIME FROM 0% DUTY CYCLE TO 100% DUTY CYCLE) 52.53 26.52 17.595 10.455 6.63 4.59 2.55 1.275
RRX-[2:0] 000 001 010 011 100 101 110 111
TIME PER PWM STEP (PWM STEP SIZE = 1/255) 206 msec 104 msec 69 msec 41 msec 26 msec 18 msec 10 msec 5 msec
PWM RAMP RATE (HZ) 4.85 9.62 14.49 24.39 38.46 55.56 100 200
8.2.16
Registers 64-66h: Minimum PWM Duty Cycle
Table 8.30 Registers 64-66h: Minimum PWM Duty Cycle
Register Address 64h 65h 66h
Read/ Write R/W R/W R/W
Register Name PWM1 Minimum Duty Cycle PWM2 Minimum Duty Cycle PWM3 Minimum Duty Cycle
Bit 7 (MSb) 7 7 7
Bit 6 6 6 6
Bit 5 5 5 5
Bit 4 4 4 4
Bit 3 3 3 3
Bit 2 2 2 2
Bit 1 1 1 1
Bit 0 (LSb) 0 0 0
Default Value 80h 80h 80h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. These registers specify the minimum duty cycle that the PWM will output when the measured temperature reaches the Temperature LIMIT register setting in Auto Fan Control Mode. Table 8.31 PWM Duty vs. Register Setting MINIMUM PWM DUTY 0% . . . 25% . . . 50% . . . 100% VALUE (DECIMAL) 0 . . . 64 . . . 128 . . . 255 VALUE (HEX) 00h . . . 40h . . . 80h . . . FFh
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8.2.17
Registers 67-69h: Zone Low Temperature Limit
Table 8.32 Registers 67-69h: Zone Low Temperature Limit
Register Address 67h 68h 69h
Read/ Write R/W R/W R/W
Register Name Zone 1 Low Temp Limit Zone 2 Low Temp Limit Zone 3 Low Temp Limit
Bit 7 (MSb) 7 7 7
Bit 6 6 6 6
Bit 5 5 5 5
Bit 4 4 4 4
Bit 3 3 3 3
Bit 2 2 2 2
Bit 1 1 1 1
Bit 0 (LSb) 0 0 0
Default Value 80h 80h 80h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. These are the temperature limits for the individual zones. When the current temperature equals this limit, the fan will be turned on if the Minimum PWM is set to 00h. When the temperature exceeds this limit, the fan speed will be increased according to the auto fan algorithm based on the setting in the Zone x Range / PWMx Frequency register. Default = -127C=80h APPLICATION NOTE: All three Zone Low Temperature Limit registers must be programmed to a valid value (other than 80h) to allow the AutoFan control to operate. Table 8.33 Temperature Limit vs. Register Setting LIMIT -127c . . . -50c . . . 0c . . . 50c . . . 127c LIMIT (DEC) -127 . . . -50 . . . 0 . . . 50 . . . 127 LIMIT (HEX) 81h . . . CEh . . . 00h . . . 32h . . . 7Fh
8.2.18
Registers 6A-6Ch: Absolute Temperature Limit
Table 8.34 Registers 6A-6Ch: Absolute Temperature Limit
Register Address 6Ah 6Bh 6Ch
Read/ Write R/W R/W R/W
Register Name Zone 1 Temp Absolute Limit Zone 2 Temp Absolute Limit Zone 3 Temp Absolute Limit
Bit 7 (MSb) 7 7 7
Bit 6 6 6 6
Bit 5 5 5 5
Bit 4 4 4 4
Bit 3 3 3 3
Bit 2 2 2 2
Bit 1 1 1 1
Bit 0 (LSb) 0 0 0
Default Value 64h 64h 64h
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These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. In Auto Fan mode, if any zone associated with a PWM output exceeds the temperature set in the Absolute limit register, all PWM outputs will increase their duty cycle to 100% except those that are disabled via the PWM Configuration registers. This is a safety feature that attempts to cool the system if there is a potentially catastrophic thermal event. If an absolute limit register set to 80h (-128c), the safety feature is disabled for the associated zone. That is, if 80h is written into the Zone x Temp Absolute Limit Register, then regardless of the reading register for the zone, the fans will not turn on-full based on the absolute temp condition. Default =100C=64h. When any fan is in auto fan mode, then if the temperature in any zone exceeds absolute limit, all fans go to full, including any in manual mode, except those that are disabled. Therefore, even if a zone is not associated with a fan, if that zone exceeds absolute, then all fans go to full. In this case, the absolute limit can be chosen to be 7Fh for those zones that are not associated with a fan, so that the fans won't turn on unless the temperature hits 127 degrees. Table 8.35 Absolute Limit vs. Register Setting ABSOLUTE LIMIT -127c . . . -50c . . . 0c . . . 50c . . . 127c ABS LIMIT (DEC) -127 . . . -50 . . . 0 . . . 50 . . . 127 ABS LIMIT (HEX) 81h . . . CEh . . . 00h . . . 32h . . . 7Fh
8.2.19
Register 6F: XOR Test Register
Table 8.36 Register 6F: XOR Test Register
Register Address 6Fh
Read/ Write R/W
Register Name XOR Test Register
Bit 7 (MSb) RES
Bit 6 RES
Bit 5 RES
Bit 4 RES
Bit 3 RES
Bit 2 RES
Bit 1 RES
Bit 0 (LSb) XEN
Default Value 00h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. The part incorporates an XOR tree test mode. When the test mode is enabled by setting the `XEN' bit high via SMBus, the part enters XOR test mode. The following signals are included in the XOR test tree: TACH1, TACH2, TACH3, TACH4
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PWM2, PWM3 Since the test mode is XOR tree, the order of the signals in the tree is not important. SDA and SCL are not included in the test tree.
8.2.20
Register 7Ch: Special Function Register
Table 8.37 Register 7Ch: Special Function Register
Register Address 7Ch
Read/ Write R/W
Register Name Special Function
Bit 7 (MSb) AVG2
Bit 6 AVG1
Bit 5 AVG0
Bit 4 SMSC
Bit 3 SMSC
Bit 2 INTEN
Bit 1 MONMD
Bit 0 (LSb) LPMD
Default Value 40h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. This register contains the following bits:
Table 8.38 Special Function Register
BIT 0 NAME LPMD R/W R/W DEFAULT 0 Low Power Mode Select. `0' = Sleep Mode `1' = Low Power Mode Monitoring Mode Select. `0' = Continuous Mode `1' = Cycle Mode Global Interrupt enable. When set enables the INT# pin output function. SMSC - writing this bit may have undesired affects. SMSC - writing this bit may have undesired affects. The AVG[2:0] bits determine the amount of averaging for each of the six measurements that are performed by the hardware monitor before the reading registers are updated (Table 8.39, "AVG[2:0] Bit Decoder"). The AVG[2:0] bits are priority encoded where the most significant bit has highest priority. For example, when the AVG2 bit is asserted, 32 averages will be performed for each measurement before the reading registers are updated regardless of the state of the AVG[1:0] bits. Note:
.
DESCRIPTION
1
MONMD
R/W
0
2 3 4 5 6 7
INTEN SMSC SMSC AVG0 AVG1 AVG2
R/W R/W R/W R/W R/W R/W
0 0 0 0 1 0
The default for the AVG[2:0] bits is `010'b
Table 8.39 AVG[2:0] Bit Decoder SFTR[7:5] AVERAGES PER READING ALL VOLTAGE READINGS ( VCCP, AND VCC) 8 1 16 32
AVG2 0 0 0 1
AVG1 0 0 1 X
AVG0 0 1 X X
REM DIODE 1 128 16 16 32
REM DIODE 2 128 16 16 32
INTERNAL DIODE 8 1 16 32
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8.2.21
Register 7Eh: Interrupt Enable 1 Register
Table 8.40 Register 7Eh: Interrupt Enable 1 Register
Register Address 7Eh
Read/ Write R/W
Register Name Interrupt Enable 1 (Voltages)
Bit 7 (MSb) VCC
Bit 6 RES
Bit 5 RES
Bit 4 RES
Bit 3 VCCP
Bit 2 RES
Bit 1 RES
Bit 0 (LSb) VOLT
Default Value ECh
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no effect. This register is used to enable individual voltage error events to set the corresponding status bits in the interrupt status registers. This register also contains the group voltage enable bit (Bit[0] VOLT), which is used to enable voltage events to force the interrupt pin (INT#) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at offset 7Ch). See Figure 6.3 Interrupt Control on page 24. This register contains the following bits:
Table 8.41 Interrupt Enable 1 Register bits
BIT 0 1 2 3 4 5 6 7 NAME VOLT Reserved Reserved VCCP Reserved Reserved Reserved VCC R/W R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 0 1 1 0 1 1 1 DESCRIPTION Group INT# Voltage Enable - when set, enables out-of-limit voltages to drive the INT# pin low (provided that the INTEN bit in the Special Function register is also set). Reserved Reserved When set Enables VCCP Channel to update status registers and generate interrupts Reserved Reserved Reserved When set, enables VCC channel to update status registers and generate interrupts.
8.2.22
Register 7Fh: Configuration Register
Table 8.42 Register 7Fh: Configuration Register
Register Address 7Fh
Read/ Write R/W
Register Name Configuration
Bit 7 (MSb) INIT
Bit 6 SMSC
Bit 5 SMSC
Bit 4 SUREN
Bit 3 TRDY
Bit 2 RES
Bit 1 P2INT
Bit 0 (LSb) T3INT
Default Value 10h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect.
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Table 8.43 Configuration Register Bits
BIT 0 NAME T3INT R/W R/W DEFAULT 0 DESCRIPTION Determines functionality of the TACH3/INT# pin. `0' - TACH3 input `1'- INT# output Determines the functionality of the PWM2/INT# pin. `0' - PWM2 output. `1' - INT# output. Reserved Temperature Reading Ready - indicates that the temperature reading registers hold valid values. Spin-up reduction enable - when set, this bit enables the reduction of the spin-up time based on feedback from all fan tachometers associated with each PWM. SMSC - Writing to this bit to a value different from the default value may cause unwanted results. SMSC - Writing this bit to a value different than the default value may cause unwanted results. Setting the INIT bit to `1' performs a soft reset. This bit is self-clearing. Soft Reset sets all the registers except the Reading Registers to their default values.
1
P2INT
R/W
0
2 3 4 5 6 7
Reserved TRDY SUREN SMSC SMSC INIT
R/W R R/W R/W R/W R/W
0 0 1 0 0 0
This register contains the following bits:
8.2.23
Register 80h: Interrupt Enable 2 Register
Table 8.44 Register 80h: Interrupt Enable 2 Register
Register Address 80h
Read/ Write R/W
Register Name Interrupt Enable 2 (Fan Tachs)
Bit 7 (MSb) RES
Bit 6 RES
Bit 5 RES
Bit 4 TACH4
Bit 3 TACH3
Bit 2 TACH2
Bit 1 TACH1
Bit 0 (LSb) TACH
Default Value 1Eh
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This register is used to enable individual fan tach error events to set the corresponding status bits in the interrupt status registers. This register also contains the group fan tach enable bit (Bit[0] TACH), which is used to enable fan tach events to force the interrupt pin (INT#) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at offset 7Ch). See Figure 6.3 Interrupt Control on page 24. This register contains the following bits:
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Table 8.45 Interrupt Enable 2 Register Bits
BIT 0 1 2 3 4 5 6 7 NAME TACH TACH1 TACH2 TACH3 TACH4 RES RES RES R/W R R R R R R/W R/W R/W DEFAULT 0 1 1 1 1 0 0 0 DESCRIPTION Group TACH INT# enable- When set enables out-of-limit TACH measurements assert the INT# pin. When set, enables the TACH1 tachometer to update status registers and generate interrupts. When set, enables the TACH2 tachometer to update status registers and generate interrupts. When set, enables the TACH3 tachometer to update status registers and generate interrupts. When set, enables the TACH4 tachometer to update status registers and generate interrupts. Reserved Reserved Reserved
8.2.24
Register 81h: TACH_PWM Association Register
Table 8.46 Register 81h: TACH_PWM Association Register
Register Address 81h
Read/ Write R/W
Register Name TACH_PWM Association
Bit 7 (MSb) T4H
Bit 6 T4L
Bit 5 T3H
Bit 4 T3L
Bit 3 T2H
Bit 2 T2L
Bit 1 T1H
Bit 0 (LSb) T1L
Default Value A4h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This register is used to associate a PWM with a tachometer input. This association is used by the fan logic to determine when to prevent a bit from being set in the interrupt status registers. The fan tachometer will not cause a bit to be set in the interrupt status register: g. if the current value in Current PWM Duty registers is 00h or h. if the fan is disabled via the Fan Configuration Register. Note: A bit will never be set in the interrupt status for a fan if its tachometer minimum is set to FFFFh. See bit definition below.
Table 8.47 TACH_PWM Association Register Bits
BIT 0 1 2 3 4 5 6 7 NAME T1L T1H T2L T2H T3L T3H T4L T4H R/W R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 0 1 0 0 1 0 1 DESCRIPTION Determine which PWM outputs are associated with the TACH1 input. See Table 8.48 Determine which PWM outputs are associated with the TACH2 input. See Table 8.48 Determine which PWM outputs are associated with the TACH3 input. See Table 8.48 Determine which PWM outputs are associated with the TACH4 input. See Table 8.48
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Table 8.48 PWM Assignment Bit Combinations
Bits[1:0], Bits[3:2], Bits[5:4], Bits[7:6] 00 01 10 11 Notes: Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1. All TACH inputs must be associated with a PWM output. If the tach is not being driven by the associated PWM output it should be configured to operate in Mode 1 and the associated TACH interrupt must be disabled. PWM Associated With Tachx PWM1 PWM2 PWM3 Reserved
8.2.25
Register 82h: Interrupt Enable 3 Register
Table 8.49 Register 82h: Interrupt Enable 3 Register
Register Address 82h
Read/ Write R/W
Register Name Interrupt Enable 3 (Temp)
Bit 7 (MSb) RES
Bit 6 RES
Bit 5 RES
Bit 4 RES
Bit 3 D2EN
Bit 2 D1EN
Bit 1 AMB
Bit 0 (LSb) TEMP
Default Value 0Eh
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect. This register is used to enable individual thermal error events to set the corresponding status bits in the interrupt status registers. This register also contains the group thermal enable bit (Bit[0] TEMP), which is used to enable thermal events to force the interrupt pin (INT#) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at offset 7Ch). See Figure 6.3 Interrupt Control on page 24. This register contains the following bits:
:
Table 8.50 Interrupt Enable 3 Register Bits
BIT 0 1 2 3 4 5 6 7 NAME TEMP AMB D1EN D2EN RES RES RES RES R/W R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 1 1 1 0 0 0 0 DESCRIPTION Group Temperature enable bit - when set, allows Temperature channels to assert the INT# pin. When set, enables the ambient temperature monitor to update the status registers and generate interrupts. When set, enables the Remote Diode 1 temperature monitor to update the status registers and generate interrupts. When set, enables the Remote Diode 2 temperature monitor to update the status registers and generate interrupts. Reserved Reserved Reserved Reserved
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8.2.26
Registers 85h-88h: A/D Converter LSbs Registers
Table 8.51 Registers 85h-88h: A/D Converter LSbs Registers
Register Address 85h 86h 88h
Read/ Write R R R
Register Name A/D Converter LSbs Reg 1 A/D Converter LSbs Reg 2 A/D Converter LSbs Reg 4
Bit 7 (MSb) RD2.3 RES VCC.3
Bit 6 RD2.2 RES VCC.2
Bit 5 RD2.1 RES VCC.1
Bit 4 RD2.0 RES VCC.0
Bit 3 RD1.3 AM.3 VCP.3
Bit 2 RD1.2 AM.2 VCP.2
Bit 1 RD1.1 AM.1 VCP.1
Bit 0 (LSb) RD1.0 AM.0 VCP.0
Default Value N/A N/A N/A
There is a 10-bit Analog to Digital Converter (ADC) located in the hardware monitoring block that converts the measured voltages into 10-bit reading values. Depending on the averaging scheme enabled, the hardware monitor may take multiple readings and average them to create the values stored in the reading registers (i.e., 16x averaging, 32x averaging, etc.) The 8 MSb's of the reading values are placed in the Reading Registers. When the upper 8-bits located in the reading registers are read the 4 LSb's are latched into their respective bits in the A/D Converter LSbs Register. This give 12-bits of resolution with a minimum value of 1/16th per unit measured. (i.e., Temperature Range: -127.9375 C < Temp < 127.9375 C and Voltage Range: 0 < Voltage < 256.9375) . See the DC Characteristics for the accuracy of the reading values. The eight most significant bits of the 12-bit averaged readings are stored in Reading registers and compared with Limit registers. The Interrupt Status Register bits are asserted if the corresponding measured value(s) on the inputs violate their programmed limits.
8.2.27
Register Address 90h 91h 92h 93h
Registers 90h-93h: TachX Option Registers
Read/ Write R/W R/W R/W R/W Register Name Tach1 Option Tach2 Option Tach3 Option Tach4 Option Bit 7 (MSb) Bit 6 RESERVED RESERVED RESERVED RESERVED Bit 5 Bit 4 3EDG 3EDG 3EDG 3EDG Bit 3 MODE MODE MODE MODE Bit 2 EDG1 EDG1 EDG1 EDG1 Bit 1 EDG0 EDG0 EDG0 EDG0 Bit 0 (LSb) SLOW SLOW SLOW SLOW Default Value 04h 04h 04h 04h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect.
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Table 8.52 TACH Option Register Bits
BIT 0 NAME SLOW R/W R/W DEFAULT 0 DESCRIPTION `0' - Force TACH reading register to FFFEh detected is greater than 0 but less than the edges `1' - Force TACH reading register to FFFFh detected is greater than 0 but less than the edges if number of tach edges programmed number of if number of tach edges programmed number of
1 2
EDG0 EDG1
R/W R/W
0 1
Determines the number of edges necessary for a valid TACH reading. 00 = 2 edges 01 = 3 edges 10 = 5 edges 11 = 9 edges Determines TACH reading mode `0' Mode 1 - standard operating mode `1' Mode 2 - only check measure TACH while PWM output is high. This bit is used when the TACH Mode is configured for Mode 2 only. `0' - don't ignore 1st 3 TACH edges after PWM transitions from low to high `1' - ignore first 3 edges after guard time Note: This bit has been added to support a small sampling of fans that emit irregular tach pulses when the PWM transitions `ON'. Typically, the guard time is sufficient for most fans.
3
MODE
R/W
0
4
3EDG
R/W
0
5 6 7
RES RES RES
R/W R/W R/W
0 0 0
Reserved Reserved Reserved
8.2.28
Registers 94h-96h: PWMx Option Registers
Table 8.53 Registers 94h-96h: PWMx Option Registers
Register Address 94h 95h 96h
Read/ Write R/W R/W R/W
Register Name PWM1 Option PWM2 Option PWM3 Option
Bit 7 (MSb) RES RES RES
Bit 6 RES RES RES
Bit 5 OPP OPP OPP
Bit 4 GRD1 GRD1 GRD1
Bit 3 GRD0 GRD0 GRD0
Bit 2 SZEN SZEN SZEN
Bit 1 UPDT1 UPDT1 UPDT1
Bit 0 (LSb) UPDT0 UPDT0 UPDT0
Default Value 0Ch 0Ch 0Ch
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have no effect.
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Table 8.54 PWM Option Register Bits
BIT 0 1 NAME UPDT0 UPDT1 R/W R/W R/W DEFAULT 0 0 DESCRIPTION Determines the update rate of tachometer circuits associated with this PWM driver. 00 - once a second 01 - twice a second 1x - every 300msec. Snap to Zero - determines if the PWM output ramps down to 00hor if is immediately set to 00h when the input is set to 00h. `0' - Step down the PWM output to OFF at the programmed ramp rate. `1' - Transition PWM output to OFF immediately when the duty cycle is set to 00h. Sets the Guard time that the tachometer associated with this PWM driver will wait after a transition from low to high before it begins measuring. 00 = 63 clocks (90kHz clock ~ 700us) 01 = 32 clocks (90kHz clock ~356us) 10 = 16 clocks (90kHz clock ~178us) 11 = 8 clocks (90kHz clock ~89us) Opportunistic Mode enable - when set, enables opportunistic mode. The tachometer reading is updated any time a valid tachometer reading can be made. If a valid reading is detected prior to the update cycle, then the update counter is reset. Reserved Reserved
2
SZEN
R/W
1
3 4
GRD0 GRD1
R/W R/W
1 0
5
OPP
R/W
0
6 7
RES RES
R/W R/W
0 0
Table 8.55 PWM/TACH Test Register Bits
BIT 0 NAME glitch R/W R/W DEFAULT 1 DESCRIPTION is used to select the glitch suppression logic on the tachometer inputs `0' TACH inputs are synchronized to 90kHz oscillator. `1' TACH inputs are deglitched and synchronized to 90kHz oscillator Determine how each PWM outputs exit SpinUp. `0' - Exit Spinup Asynchronously to the PWM duty cycle. The first PWM period when SpinUP is terminate may be a partial period. `1' - Exit Spinup at the beginning of the next PWM duty cycle period. This option gets rid of the initial partial period created by exiting SpinUp, but it extends the SpinUp time beyond the programmed limit. Determines the rollover value for mode 1 (all Tachs) `0' 0080h - useful for simulation `1' FFFFh Scale the PWM duty cycle for the corresponding channel. When enabled, will shift the PWM duty cycle down by 2 creating a duty cycle with a resolution of 1/256. This allows the device to support higher PWM frequencies `0'= 64 count PWM duty cycle - resolution is 1/64 `1' = 256 count PWM duty cycle
1 2 3
PSYNC1 PSYNC2 PSYNC3
R/W R/W R/W
0 0 0
4 5 6 7
ROVR PWM1_256/ 64 PWM2_256/ 64 PWM3_256/ 64
R/W R/W R/W R/W
1 1 1 1
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Chapter 9 Timing Diagrams
9.1 PWM Outputs
The following section shows the timing for the PWM[1:3] outputs.
t1 FANx t2
Figure 9.1 PWMx Output Timing Table 9.1 Timing for PWM[1:3] Outputs NAME t1 t2 DESCRIPTION PWM Period (Note 9.2) PWM High Time (Note 9.3) Note 9.2 Note 9.3 MIN 0.04 0 TYP MAX 90.9 99.6 UNITS msec %
This value is programmable by the PWM frequency bits located in the FRFx registers. The PWM High Time is based on a percentage of the total PWM period (min=0/256*TPWM, max =255/256*TPWM). During Spin-up the PWM High Time can reach a 100% or Full On. (TPWM = t1).
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9.2
SMBus Interface
tLOW tR tF tHD;STA
SCLK tHD;STA tHD;DAT tSU;STA tSU;STO
tHIGH
tSU;DAT
SDA tBUF P S S P
Figure 9.4 SMBus Timing Table 9.2 SMBus Timing LIMITS SYMBOL Fsmb Tsp Tbuf Thd:sta PARAMETER SMB Operating Frequency Spike Suppression Bus free time between Stop and Start Condition Hold time after (Repeated) Start Condition. After this period, the first clock is generated. Repeated Start Condition setup time Stop Condition setup time Data hold time Data setup time Clock low period Clock high period Clock/Data Fall Time Clock/Data Rise Time Capacitive load for each bus line Note 9.5 1.3 0.6 10 MIN MAX 400 50 UNITS kHz ns
s s
COMMENTS Note 9.5 Note 9.6
Tsu:sta Tsu:sto Thd:dat Tsu:dat Tlow Thigh Tf Tr Cb
0.6 0.6 0.3 100 1.3 0.6 20+0.1Cb 20+0.1Cb 300 300 400 0.9
s s s
ns
s s
Note 9.7
ns ns pF
The SMBus timing (e.g., max clock frequency of 400kHz) specified exceeds that specified in the System Management Bus Specification, Rev 1.1. This corresponds to the maximum clock frequency for fast mode devices on the I2C bus. See "The I2C Bus Specification," version 2.0, Dec. 1998. At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input filter. If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns (1000 ns (TR max) + 250 ns (TSU:DAT min) @ 100 kHz) before the SCLK line is released.
Note 9.6 Note 9.7
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Chapter 10 Mechanical Specifications
REVISION HISTORY
REVISION A DESCRIPTION INITIAL RELEASE DATE 8/02/024 RELEASED BY S.K.ILIEV
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Datasheet
Fan Control Device with High Frequency PWM and Temperature Monitors
D e 16
3
SEE DETAIL "A"
3
E1
E
12 5 INDEX AREA (D/2 X E1/2) 4 8X b 2 4 c
TOP VIEW
END VIEW
C A2 SEATING PLANE ccc C A
A1
SIDE VIEW
3-D VIEW
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETER. 2. TRUE POSITION SPREAD TOLERANCE IS 0.09 mm AT MAXIMUM MATERIAL CONDITION. 3. DIMENSION "D" DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MAXIMUM MOLD FLASH, PROTRUSIONS OR GATE BURRS IS 0.15 mm PER END. DIMENSION "E1" DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. MAXIMUM INTERLEAD FLASH OR PROTRUSION IS 0.15 mm PER SIDE. DIMENSIONS "D1" & "E1" ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY, INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM BODY. 4. DIMENSIONS "b" & "c" APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP. 5. THE CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED.
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND TOLERANCES ARE: DECIMAL 0.1 X.X X.XX 0.05 X.XXX 0.025 ANGULAR 1
THIRD ANGLE PROJECTION
0.25 GAUGE PLANE
L L1
0
80 ARKAY DRIVE HAUPPAUGE, NY 11788 USA
DETAIL "A"
SCALE: 3/1
TITLE
DIM AND TOL PER ASME Y14.5M - 1994
MATERIAL
NAME
DRAWN
DATE
-
S.K.ILIEV
CHECKED
7/30/04 8/02/04
SCALE
PACKAGE OUTLINE 16 PIN SSOP, 150x193mils BODY, 0.025" PITCH
DWG NUMBER
FINISH
S.K.ILIEV
APPROVED
MO-16-SSOP-150x193
STD COMPLIANCE SHEET
REV
A 1 OF 1
PRINT WITH "SCALE TO FIT" DO NOT SCALE DRAWING
S.K.ILIEV
8/02/04
1:1
JEDEC: MO-137 / B
Figure 10.1 16 Pin SSOP Package Outline and Parameters
Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
Appendix A ADC Voltage Conversion
Table A.1 Analog-to-Digital Voltage Conversions for Hardware Monitoring Block
INPUT VOLTAGE VCC <0.0172 0.017-0.034 0.034-0.052 0.052-0.069 0.069-0.086 0.086-0.103 0.103-0.120 0.120-0.138 0.138-0.155 ... 1.100-1.117 ... 2.200-2.217 ... 3.300-3.317 ... 4.210-4.230 4.230-4.245 4.245-4.263 4.263-4.280 4.280-4.300 4.300-4.314 4.314-4.330 4.331-4.348 4.348-4.366 4.366-4.383 >4.383 VCCPIN <0.012 0.012-0.023 0.023-0.035 0.035-0.047 0.047-0.058 0.058-0.070 0.070-0.082 0.082-0.093 0.093-0.105 ... 0.749-0.761 ... 1.499-1.511 ... 2.249-2.261 ... 2.869-2.881 2.881-2.893 2.893-2.905 2.905-2.916 2.916-2.928 2.928-2.940 2.940-2.951 2.951-2.964 2.964-2.975 2.975-2.987 >2.988 Decimal 0 1 2 3 4 5 6 7 8 ... 64 (1/4 Scale) ... 128 (1/2 Scale) ... 192 (3/4 Scale) ... 245 246 247 248 249 250 251 252 253 254 255 A/D OUTPUT Binary 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 ... 0100 0000 ... 1000 0000 ... 1100 0000 ... 1111 0101 1111 0110 1111 0111 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111
Revision 0.2 (06-14-06)
DATASHEET
78
SMSC EMC2300
Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
Appendix B Example Fan Circuits
The following figures show examples of circuitry on the board for the PWM outputs, tachometer inputs, and remote diodes. Figure B.1, "Fan Drive Circuitry (Apply to PWM Driving Two Fans)" shows how the part can be used to control four fans by connecting two fans to one PWM output. Note: These examples represent the minimum required components. Some designs may require additional components.
3.3V
3.3V
12 V
1k
PWMx
2.2k
MMBT390 4
M
MMBT222 2 Fan 1
M
MMBT222 2 Fan 2
Figure B.1 Fan Drive Circuitry (Apply to PWM Driving Two Fans)
SMSC EMC2300
DATASHEET
79
Revision 0.2 (06-14-06)
Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
3.3V
12V
470
Fan
PWMx
MMBT2222
M
Figure B.2 Fan Drive Circuitry (Apply to PWM Driving One Fan)
3.3V
Tach Output from Fan
D1 IN4148
10k
TACH Input
Note: For fans controlled directly by a PW M , it is suggested to im plem ent the optional diode (D1) to protect the tachom eter input from large voltage spikes generated by the fan.
Figure B.3 Fan Tachometer Circuitry (Apply to Each Fan)
Revision 0.2 (06-14-06)
DATASHEET
80
SMSC EMC2300
Fan Control Device with High Frequency PWM and Temperature Monitors
Datasheet
Remote Diode +
2.2nF
External Temperature Sensing Diode (MMBT3904)
Remote Diode -
Figure B.4 Remote Diode (Apply to Remote2 Lines)
Notes: 1. 2.2nF cap is optional and should be placed close to the EMC2300 if used. 2. The voltage at PWM3 must be at least 2.0V to avoid triggering Address Enable. 3. The Remote Diode + and Remote Diode - tracks should be kept close together, in parallel with grounded guard tracks on each side. Using wide tracks will help to minimize inductance and reduce noise pickup. A 10 mil track minimum width and spacing is recommended. See Figure B.5, "Suggested Minimum Track Width and Spacing".
.
GND D+ DGND
10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil.
Figure B.5 Suggested Minimum Track Width and Spacing
SMSC EMC2300
DATASHEET
81
Revision 0.2 (06-14-06)

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